M451
May. 4, 2018
Page
437
of
1006
Rev.2.08
M4
51
S
E
RI
E
S
T
E
CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
6.9.3 Block Diagram
A
P
B
PWM0
PWM0_BRAKE0
PWM0_BRAKE1
PWM0_SYNC_IN
SYNC_IN
SYNC_IN
SYNC_OUT
PWM1_BRAKE0
PWM1_BRAKE1
TIMER0
EADC
CLOCK
CONTROLLER
5
PWM1
TIMER1
TIMER2
TIMER3
SYNC_IN
DAC
PDMA
PWM0_CH0
PWM0_CH5
4
4
NVIC_MUX
3
3
6
6
PWM1_CH5
PWM1_CH0
Note:
Only capture
mode output to PDMA
Clock Fail
ACMP
Brown-Out Detect
SRAM Parity Error
CPU Lockup
Brake Source
6
PWM0_SYNC_OUT
Figure 6.9-1 PWM Generator Overview Block Diagram
PWM system clock frequency can be set equal or double to HCLK frequency as Figure 6.9-2, the
detail register setting, please refer to Table 6-13.
Each PWM generator has three clock source inputs, each clock source can be selected from system
clock or four TIMER trigger PWM outputs as Figure 6.9-3 by ECLKSRC0 (PWM_CLKSRC[2:0]) for
PWM_CLK0, ECLKSRC2 (PWM_CLKSRC[10:8]) for PWM_CLK2 and ECLKSRC4
(PWM_CLKSRC[18:16]).
HCLKSEL
(CLK_CLKSEL0[2:0])
1/(1)
HCLK
0
1
0
1
PWM0
system clock
PWM1
system clock
PCLK0
PCLK1
PWM1SEL (CLK_CLKSEL2[1])
PWM0SEL (CLK_CLKSEL2[0])
PWM0CKEN (CLK_APBCLK1[16])
PWM1CKEN (CLK_APBCLK1[17])
HCLKDIV (CLK_CLKDIV0[3:0])
0
1
2
3
7
HXT
LXT
PLL
LIRC
HIRC
Figure 6.9-2 PWM System Clock Source Control
