Registers Format
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Registers Format
The registers format of ACL-7225 is described in this chapter.
3.1 Registers Map
The ACL-7225 requires 8 consecutive addresses (only 4 are used) in
the PC I/O address space. The following table (Table 3.1) shows the
location of each register and driver relative to the base address, and its
description.
Location
FUNCTION DESCRIPTION
R/W Attribute
Base + 0
Relay Outputs (R0~R7)
Read/Write
Base + 1
Relay Outputs (R8~R15)
Read/Write
Base + 2
Isolated Inputs (DI0 ~DI7)
Read Only
Base + 3
Isolated Inputs (DI8 ~DI15)
Read Only
Base + 4
Not Used
-
Base + 5
Not Used
-
Base + 6
Not Used
-
Base + 7
Not Used
-
Table 3.1 I/O Registers Map
3.2 Relay Output Registers
The ACL-7225 provides 16 relay output channels, and they are arranged
into two groups. First group relays(R0 ~R7) are controlled via the
register Base + 0, and the second group relays ( R8~R15) are controlled
via the register Base + 1. The ON/OFF status of each relay is controlled
by its corresponding one bit of register, i.e. the control bit is low (0)
status, it turns the relay OFF, and high status (1) will energized the relay.