NR Electric PCS-9611, Instruction Manual

Page: 86 / 300

3 Operation Theory
PCS-9611 Feeder Relay
3-50
Date: 2014-04-08
[81U1.Op]
Uca > [81.Upp_VCE]
Ubc > [81.Upp_VCE]
Uab > [81.Upp_VCE]
&
&
[81U1.Blk]
f < [81U1.f_Set]
[81U1.En]
[81U1.En1]
[81U1.St]
t
UF1
0
Figure 3.16-1 Logic diagram of the stage 1 under-frequency protection
Where:
[81U1.f_Set] is the frequency setting of the stage 1 under-frequency protection;
“t
UF1
” is the setting [81U1.t_Op], the time setting of the stage 1 under-frequency protection;
[81.Upp_VCE] is the under voltage blocking setting of the frequency protection;
[81U1.En] is the logic setting of the stage 1 under-frequency protection;
[81U1.En1] is the binary signal for enabling the stage 1 under-frequency protection;
[81U1.Blk] is the binary signal for blocking the stage 1 under-frequency protection.
3.16.2 Over-frequency Protection
The feeder relay provides a four-stage over-frequency protection with independent definite time
delay characteristics, and the four stages have same protection logics.
This protection can be enabled after 100ms only when the frequency is less than the frequency
setting [81Ox.f_Set] (x: 1~4) and three phase-to-phase voltages are greater than the setting
[81.Upp_VCE]. Meanwhile, this protection will be blocked when the system frequency is less than
“f
n
-15.00Hz
” or greater than “f
n
+15.00Hz
” for longer than 200ms (f
n
: system rated frequency).
The logic diagram of the stage 1 over-frequency protection is shown as below.
[81O1.Op]
Uca > [81.Upp_VCE]
Ubc > [81.Upp_VCE]
Uab > [81.Upp_VCE]
&
&
[81O1.Blk]
f > [81O1.f_Set]
[81O1.En]
[81O1.En1]
[81O1.St]
t
OF1
0
Figure 3.16-2 Logic diagram of the stage 1 over-frequency protection
Where:
[81O1.f_Set] is the frequency setting of the stage 1 over-frequency protection;
“t
OF1
” is the setting [81O1.t_Op], the time setting of the stage 1 over-frequency protection;
[81.Upp_VCE] is the under voltage blocking setting of the frequency protection;
[81O1.En] is the logic setting of the stage 1 over-frequency protection;