10
DDS9m Manual
4.14 Phase relationships are maintained by appro-
priate use of the
“M”
and
“I”
commands. The
“M”
command has special modes
“M a”
and
“M n”
.
“M a”
means automatically clear phase at the end
of each command. This will clear the phase register
each time any command is performed. This is
important when all outputs must be phase aligned.
However, it may cause a phase discontinuity in the
output.
4.15 The
“M n”
command turns off the automatic
clearing of the phase register. This is the default
mode. In this mode, the phase register is left intact
when a command is performed. Use this mode if you
want frequency changes to remain phase synchro-
nous, with no phase discontinuities.
4.16 Further control of phase relationships and tim-
ing of command execution can be exercised by
using the
“I m”
,
“I a”
and
“I p”
commands.
The default mode is
“I a”
in which a command is
parsed and executed immediately following the end
of the serial input sequence. In the
“I m”
mode, an
update pulse will not be sent to the DDS chip until
an
“I p”
command is sent. This is useful when it is
important to change all the outputs to new values
simultaneously.
4.17 For applications which require precise ampli-
tude matching between the channels, the recom-
mended method is to use the
“Vn N”
command to
adjust the channels to match the other. This com-
mand provides 10-bits of adjustment range.
4.18 High Speed Interface Operation. When the
high speed interface (P1) mode is chosen, the opera-
tion of the DDS9m is completely dependent upon
the user supplied interface circuitry. The on-board
microprocessor and software are disabled in parallel
operation. Therefore, no error conditions are
detected or reported.
NOTE:
The AD9959 pins MASTER_RESET,
PWR_DWN_CTL, CS* are set by the on-board
microcomputer at power-up and are not accessible
on the high speed interface. The table mode or table
RAM is not accessible from the high speed interface.
NOVATECH INSTRUMENTS
4.19 The on-board Voltage Controlled Temperature
Compensated Crystal Oscillator (VCTCXO) can be
adjusted approxi/-5ppm from nominal by
applying a 0 to 5Volt signal on P5. Your voltage con-
trol must be capable of sourcing and sinking 0.5mA.
Nominal voltage is approximately 2.5 Volts. This
feature is useful for applications which require
Phase Locking to external sources, using customer
supplied circuitry.
4.20 Other Modes. The DDS9m can be pro-
grammed by using the
“B”
command to perform
many other outputs. The
“B”
command can be used
to gain control over the on-board AD9959 DDS
ASIC. Refer to the Analog Device data sheet for
detailed information when using the
“B”
command.
5.0
Theory of Operation
5.1 Please refer to the simplified System Block Dia-
gram in Figure 3 for the following discussion.
5.2 At every cycle of the DDS9m master clock, the
32-bit DDS integrated circuit increments the phase
of an internal register by a value determined by the
frequency setting loaded into the on-chip registers.
This digital phase value is converted on-chip to a
sinusoidal amplitude level and delivered to on-chip
10-bit digital-to-analog converters. The analog sig-
nals from these converters are filtered by differential
7th-order elliptical low pass filters, amplified and
sent to the MCX receptacles.
5.3 The frequency generated by the DDS IC is
determined by the 32-bit frequency word loaded into
the frequency register on the DDS9m. The output
frequency is given by:
F
out
= F
setting
*Kp*F
clock
/2
32
Hz
Where:
F
clock
= 28,633,115.306666667 Hz (int.)
F
setting
= Binary value in DDS IC.
(F
setting
ranges from 0 to 2
31
-1)
Kp = PLL Multiplier (1 or 4 to 20)
This reduces to:
F
out
= F
setting
MHz
