Novametrix Medical Systems OXYPLETH 520A, Service Manual

Page: 35 / 133

2471 & 2775 Main Board
5-Jun-01 Model 520A Service Manual
25
PRELIMINARY
C100 (that maintains the signal until next sample pulse arrives), a gain stage, (IC38
pin 1), a filter/divider network (C87, R45 and R46), and finally, to the Red channel
Analog-to-Digital Convertor (ADC) IC34.
If the signal at IC40 pin 7 is the product of the Infrared LED being turned on, then
ISMP* from IC42 pin 13 will go low and close the switch at IC41 pins 14-15,
thereby presenting the signal to a sample and hold circuit consisting of R55 and C96
(that maintains the signal until next sample pulse arrives), a gain stage, (IC38 pin
7), a filter/divider network (C88, R49 and R50), and finally, to the Infrared channel
Analog-to-Digital Convertor IC37.
Again referencing Figure 3., the ASAMP* line returns to a logic high when neither
LED is being driven, causing Q15 to turn on. With Q15 conducting, any charge at
C90 is discharged to ground and the next pulse will charge C90 from a known level.
If it were not for Q15, any charge remaining on C90 from the previous pulse or from
ambient light reaching the photodiode would be added to the charge from a new
pulse—creating measurement errors.
Calibrating the 20-Bit Analog-to-Digital Convertors
9.3.10
The 20-bit ADCs are calibrated as part of the system self-test which occurs each
time the monitor is turned on. At power up, the microprocessor sets the CAL line
high. The System Calibrations input SC1 is set high and SC2 is reset to a logic low.
The CS5503 ADC will not operate while the CAL line is high. On the falling edge
of the CAL signal, the ADC will initiate a calibration cycle determined by the state
of the SC1 and SC2 inputs.
The high at SC1 and the low at SC2 cause the Data Sampling Controller, IC42, to
set INSIG* high and reset SIGND* to a logic low. The high INSIG* opens the
switch at IC41 pin8 so that IC41 pins 6 and 7 are no longer connected—
disconnecting the returning photodiode signal from the rest of the circuitry. The low
SIGND* signal closes the switch at IC41 pin9 and as a result, the input to the C90-
R59 high pass filter (and thus the entire ADC input circuitry) is brought to ground
potential.
The CAL line (which went high at power up) is reset low and ADCs IC34 and IC37
begin their calibration cycles. Because the analog input circuitry is grounded via
SIGND*, only circuit offset voltages can be present at the (pin 9 AIN) input. The
calibration cycle sets the ADC “zero” point to equal this voltage, thus compensating
for any circuitry offsets. The ADC then sets its “full scale” point to equal the voltage
at its VREF (pin 10) input. This completes the calibration cycle.
The ADC can now start sampling its input and converting it to a 20-bit digital word.
The processor resets SC1 to a logic low, causing IC41 pin9 to open and IC41 pin8
to close. The photodiode signal can now reach the ADCs. See
Sensor Photodiode
Return Path on page 24.