NOVA electronics Inc. MCX514 -
259
－
259
－
11.6
Decelerating Stop
The following figure illustrates the timing of decelerating stop. Decelerating stop signals are nSTOP2
～
0 and nLMTP/M (When
setting the decelerating stop mode).
When a decelerating stop input signal becomes active, or a decelerating stop command is written, decelerating stop will be
performed after the output of pulses being outputted.
Decelerating stop signal
nPP,nPM
DSND
Active
Decelerating stop command WRN
When the input signal filter is enabled, the input signal will be delayed according to the time constant of the filter.
11.7
Detailed Timing of Split Pulse
When with starting pulse is enabled in split pulse mode setting, only the first split pulse is on the Hi level at the timing of the drive
pulse
↑
. The second or later split pulses are on the Hi level after 1 CLK cycle from the drive pulse
↑
. Therefore, the Hi level
width of the first split pulse is 1 CLK cycle longer than that of the second or later split pulses.
When without starting pulse is enabled in split pulse mode setting, all the split pulses are on the Hi level after 1 CLK cycle from
the drive pulse
↑
(when the positive logic is set).
CLK
WRN
nPP,nPM
Without starting pulse
With starting pulse
nSPLTP
Writing a start of split pulse command
nSPLTP
↑
timing of drive pulse
After 1CLK from drive pulse
↑
After 1CLK from drive pulse
↑
１
１
２
３
２
