NorthStar HORIZON Random Access Memory User Manual Download

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HRAM

USER/TECHNICAL

MANUAL

HRAM

INTERFACE

SIGNALS

APPENDIX

Type of Signal

Signal Name

Description

Address

A15-AO

16 bits of address from

the processor

D17-DIO

8 bits of data to the

processor

Data

D07-D00

8 bits of data from the

processor

SMEMR

True on memory reads

SOUT True

output

instructions (to ports,
not to memory)

SMI

True on op-code fetches

Cycle Status

RFSH

True on refresh cycles

PDBIN

Strobes data to the
processor from memory or

port

Strobe

PWR

Strobes data from the
processor to memory or

port

V I 0

Vectored interrupt

VI1

VI2

VI3

V I 4

V I 5

VI6

VI7

NMI Non-maskable

interrupt

Interrupt

PINT Program

Interrupt:

chiefly for application
when vectored interrupts
are not used

Summary of Contents for HORIZON Random Access Memory

Page 1: ...n Leandro CA 94577 USA 415 357 8500 TWX Telex 910 366 7001 HRAM HORIZON Random Access Memory USER TECHNICAL MANUAL HORIZON is a registered trademark of North Star Computers Inc Copyright 1981 by North Star Computers Inc All Rights Reserved 004068 ...

Page 2: ...HRAM USER TECHNICAL MANUAL This manual was digitally remastered by Howard M Harte June 2003 http www hartetec com If you find any errors please email hharte hartetec com ...

Page 3: ...onfigurations 3 3 3 1 1 Example 1 Three Banks 3 3 3 1 2 Example 2 Three Banks 3 5 3 1 3 Example 3 Four Banks 3 6 3 2 Bank Switching 3 7 3 2 1 Designating Switched Areas 3 7 3 2 2 Designating I O Port Control Bit 3 9 3 2 3 Software Instructions 3 10 3 2 4 Bank Status on Reset 3 11 3 3 Memory Address Switches 3 13 3 3 1 Revision B Board 3 13 3 3 2 Revision E Board 3 14 3 3 3 32K Board 3 18 3 4 First...

Page 4: ...OF OPERATION 5 1 Overview 5 1 5 2 Address Multiplexer 5 2 5 3 Refresh Logic 5 3 5 4 Port CO Detector 5 4 5 5 Address Latch 5 4 5 6 Address Decoder 5 4 5 7 Jumper Area JP1 5 5 5 8 Bank and Parity Logic 5 5 5 9 Strobe Generator 5 6 5 10 Voltage Regulators 5 9 6 TROUBLESHOOTING 6 1 Check HRAM Seating 6 1 6 2 Change Board Slots 6 2 6 3 Check HRAM Configuration 6 2 6 4 Run Diagnostic Programs 6 2 6 5 R...

Page 5: ...HRAM USER TECHNICAL MANUAL APPENDICES A RAM Chip Location Chart A 1 B Bus Signals Used by HRAM B 1 C HRAM 64K Parts List C 1 D HRAM 64K Schematics D 1 E Reader Response Form E 1 ...

Page 6: ...HRAM USER TECHNICAL MANUAL ...

Page 7: ... There are three versions of the HRAM board HRAM 64 with 64K bytes HRAM 48 with 48K bytes and HRAM 32 with 32K bytes The only significant difference between these boards is the amount of memory they contain All three versions incorporate parity error checking and bank switching capabilities 1 2 WARRANTY North Star Computers Inc warrants the electrical and mechanical parts and workmanship of this p...

Page 8: ...er must call the North Star Technical Hotline to receive a Return Material Authorization RMA number to accompany the item to the factory The following warranty limitation applies to units located outside the United States of America All costs and arrangements for transportation of the product to and from the factory are borne entirely by the customer No warranty expressed or implied is extended co...

Page 9: ...The HRAM specifications are given in Table 1 1 Table 1 1 HRAM Specifications Storage Capacity 32K bytes for the HRAM 32 48K bytes for the HRAM 48 64K bytes for the HRAM 64 Bits per Byte Eight data bits and one parity bit Access Time 300 ns typical ...

Page 10: ...HRAM USER TECHNICAL MANUAL ...

Page 11: ...as packaged separately from the HORIZON examine the contents of the carton to make sure they match the packing slip Check to see if anything appears to be damaged due to shipping When handling the board touch it only by the edges to avoid contact with the sensitive components see Figure 2 1 When laying the board down place it on a flat surface with the components facing up Holding the HRAM Figure ...

Page 12: ...and the computer Discharging Static Electricity Figure 2 2 Hold the board by both edges with the component side of the board toward the front of the computer Slide the board into any empty slot in the HORIZON as shown in Figure 2 3 Installing the HRAM Figure 2 3 The row of metallic strips or fingers on the bottom of the board should f it into the connector at the base of the card slot Press firmly...

Page 13: ...HE POWER IS COMPLETELY OFF IN THE HORIZON To remove the HRAM grasp the upper edge of the board Avoid putting excessive pressure on the board components and be careful of the sharp wire tips that project out of the back of the board Pull the board out and lay it down on a flat surface ...

Page 14: ...HRAM USER TECHNICAL MANUAL ...

Page 15: ... the setting of the Memory Address switches Figure 3 1 shows the locations of the jumper areas and the address switches on a 64K revision E board Other boards differ as follows 1 Jumper areas JP4 and JP6 do not exist on revision B boards 2 Switch S2 is not installed on 48K revision B boards Instructions for determining the revision level of the HRAM board are given in Section 3 6 ...

Page 16: ...emory areas JP1 Selects the bank status on reset and selects I O control bits for bank switching and parity JP2 Selects areas to be bank switched JP3 Selects the parity error response JP4 Implements the First Quadrant option JP6 Reserved for future use Do not install a jumper plug at this location Figure 3 1 ...

Page 17: ... the HORIZON Make sure the power is turned off and the red light on the front panel is completely out before you remove the HRAM To reconfigure the jumper plugs lay the HRAM board down on a flat surface with the components facing up You can move the jumper plugs with your fingers or a pair of long nose pliers EXAMPLE SYSTEM CONFIGURATIONS This section shows the correct positions of the Memory Addr...

Page 18: ...of 6K that is always left on Each bank is switched off and on as a single unit Bank 1 is configured to be turned on after the system is powered up or reset Banks 2 and 3 are configured to be turned off after the system is powered up or reset Parity error checking is left in the standard North Star configuration Example 1 Figure 3 2 ...

Page 19: ...rough 7FFFH and 8000H through BFFFH An operating system that requires 16K of memory is loaded into the region between 8000H BFFFH This segment is always turned on The other segment of this board is bank switched and is designated the bank to be turned on when the system powers up or resets All three 32K boards have their memory starting at OOOOH All are bank switched off and on as single units and...

Page 20: ...HRAM USER TECHNICAL MANUAL Example 2 Figure 3 2 ...

Page 21: ...em is loaded into this half and it is always turned on All three 48K boards have their memory between 4000H and FFFFH except for the 2K section E800H through EFFFH which must be disabled to prevent interference with the Micro Disk Controller The three 48K boards constitute three banks which are switched as single units One of these banks board 2 is programmed to switch on when the system is powere...

Page 22: ...HRAM USER TECHNICAL MANUAL Example 2 Figure 3 2 ...

Page 23: ...that will not fit into a single memory bank Only one bank at a time can respond to a specific memory reference Such a bank is said to be on A bank is off when it does not respond to reads and writes from the processor Although a bank that is off cannot accept data from or provide data to the processor the stored data continues to be refreshed and remains intact 3 2 1 Designating Switched Areas For...

Page 24: ...halves of the board always on Bank switching is disabled on this board Both halves of the board bank switchable The 32K section starting at 0000H is switchable The 32K section starting at 8000H is always on The 32K section starting at 8000H is switchable The 32K section starting at 0000H is always on ...

Page 25: ...r plug that connects any B pin in JP1 to any one of the adjacent pins 1 7 allows the corresponding I O bit to program the bank switching of this board see Figure 3 5 With six I O bits available it is possible to switch on and off a maximum of six memory banks Figure 3 6 shows the position of the jumper plug on the HRAM board assigned to bank 3 Jumper Area JP1 Figure 3 5 One of bits 5 6 or 7 is use...

Page 26: ...ards in conjunction with HRAM boards to create a bank switching system 3 2 3 Software Instructions The following instructions are an example of how to turn on or off memory bank 3 Memory bank 3 is composed of all those RAM boards that are configured to use I O bit 3 for bank switching MVI A 08H Turn on bank 3 OUT 0C0H MVI A 09H Turn off bank 3 OUT 0C0H Note that bit 0 is used to specify turning th...

Page 27: ...y one bank comes on when power is first turned on When switching banks the previous bank must be switched off before the next bank is switched on 3 2 4 Bank Status on Reset The HRAM is shipped with a jumper plug in the position shown in Figure 3 7 This connection causes the bank to always remain on JP1 Set for Bank Always On Figure 3 7 ...

Page 28: ...lug s to the position shown in Figure 3 8 This will cause all the memory in this bank to be on after the system is powered up or reset JP1 Set to Enable Bank on Reset Figure 3 8 On the memory board for all other banks move the corresponding jumper plug to the position shown in Figure 3 9 These banks will be turned off when the system is powered up or reset JP1 Set to Disable Bank on Reset Figure 3...

Page 29: ...ess switches allow the HRAM Board to respond to some sections of the memory address space and not to others The correspondence between the Memory Address switches S1 and S2 on the revision B board and the address space is shown in Figure 3 10 Memory Address Switches Revision B Board Figure 3 10 ...

Page 30: ...rned off If the last 8K section is controlled by S2 individual 1K sections of the address space can be selected and the selection is independent of bank switching Any 1K section is selected if the corresponding S2 switch is on and is not selected if the switch is off This arrangement allows memory sections E8000H through EBFFH and EC00H through EFFFH to be disabled to allow space for the Disk Cont...

Page 31: ...HRAM USER TECHNICAL MANUAL Memory A dd re ss Switches Revision E Board Figure 3 11 ...

Page 32: ...ogic The last 8K section E000H through FFFFH can either be controlled as described for the other seven sections or it can be controlled by S2 If it is controlled by S1 then all of the S2 switches must be turned off If it is controlled by S2 switch E of S1 must be turned off If the last 8K section is controlled by S2 individual 2K sections of the address space can be selected by setting the corresp...

Page 33: ...itch Pair in S2 Description Corresponding 2K section is always off Corresponding 2K section is on when bank is switched off This Configuration is not normally used Corresponding 2K section is on when bank is switched on Corresponding 2K section is always on ...

Page 34: ... of address space For example if switch 0 and 8 of S1 are both on the same 8K of memory responds to addresses 0000H through 1FFFH and 8000H through 9FFFH The switches in S1 are normally configured to avoid this double selection by not having both switches in the following switch pairs on at the same time switches 0 and 8 2 and A 4 and C and 6 and E ...

Page 35: ...ess space 4000H through FFFFH instead of the first 48K 0000H through BFFFH This option is implemented by changing the jumper plugs in area JP4 Table 3 3 shows the standard and alternate positions of the jumper plugs in this area and the resulting memory configurations The shaded blocks in Table 3 3 indicate those quadrants to which the board can respond Table 3 3 The First Quadrant Option Jumper A...

Page 36: ... interrupts A jumper plug in area JP1 determines which of three possible bits of the output byte will be used to arm or disarm parity error interrupts from the memory board to the processor The HRAM is shipped with the jumper plug positioned as shown in Figure 3 12 This selects bit 6 as the control bit and is the North Star standard configuration Bits 5 or 7 may be selected by connecting pin P to ...

Page 37: ...one nonvectored interrupt PINT or one non maskable interrupt NMI As shipped the board is jumpered to select VI5 as shown in Figure 3 13 This is the North Star standard required by DOS and other operating systems JP3 Selecting Vectored Interrupt 5 Figure 3 13 If you are using other software you can pick another interrupt NMI should only be used as an emergency service technique If no interrupt is d...

Page 38: ...ondition on or off If you choose a different I O bit change the program instructions accordingly If you move the mini jump in JP1 to select bit 5 instead of bit 6 the operands should change from 41H and 40H to 21H and 20H If you select bit 7 the operands should change from 41H and 40H to 81H and 80H 3 6 BOARD AND SCHEMATIC REVISION LEVELS To determine the revision level of the HRAM board look on t...

Page 39: ...le to test the HRAM board before actually using it To test the HRAM install it in a HORIZON system and run the RAMTEST3 or RAMTEST5 diagnostic programs These programs are on the DOS 5 2 diskette They are described in the System Software Manual Addendum dated July 1980 ...

Page 40: ...HRAM USER TECHNICAL MANUAL ...

Page 41: ...h of these 9 bit bytes is then stored in one of the blocks of RAM chips The HRAM uses odd parity The design of the HRAM is based on the 16K x 1 dynamic RAM chip known as the 4116 These chips are arranged in rows to form 16K 9 bit bytes The HRAM 64 contains four rows of RAM chips the HRAM 48 has three rows and the HRAM 32 has two rows Since each byte includes a ninth bit for parity error checking t...

Page 42: ...HRAM USER TECHNICAL MANUAL HRAM Block Diagram Figure 5 1 ...

Page 43: ...s memory address bits AO through A13 and sends these bits to the Memory Array 7 bits at a time Bits AO through A6 become the row address for the RAM chips and bits A7 through A13 become the column address 5 3 REFRESH LOGIC The Refresh Logic supplies the RAM array with a 7 bit address on each memory refresh cycle The address determines which row of cells in the RAM chips is to be refreshed on that ...

Page 44: ...emory address the E6 and E8 signals from the Parity and Bank Switching Logic and the setting of the Memory Address switches Sl and S2 Signal I N is low when the HRAM board is allowed to respond to addresses in the range 0000H through 7FFFH Signal E performs the same function for the address range 8000H through FFFFH The Address Decoder Sets the SEL signal high if the memory address is within a ban...

Page 45: ...the parity error checking see Section 3 5 1 and 3 5 3 5 8 BANK AND PARITY CONTROL LOGIC The Bank and Parity Control Logic performs the following functions 1 It responds to program commands to switch the memory bank in the HRAM board on and off see Section 3 2 2 and 3 2 3 The resulting OCCLUDE signal is high when the bank is switched off and low when the bank is switched on 2 It determines how much...

Page 46: ...s VI0 THROUGH VI7 NMI and PINT 5 9 STROBE GENERATOR The Strobe Generator produces various strobes and timing pulses used throughout the HRAM board It also selects one of the four possible rows of RAM chips each time the RAM array is accessed The basic timing for the Strobe Generator is produced by a 5 stage delay module which is triggered when the START signal goes high The timing of the module ou...

Page 47: ... the memory address selects the row address strobes as shown in Table 5 1 Table 5 1 Chip Selection 64K OR 48K First Quadrant Option Inactive RAM Chip Locations Address Range Row Address Strobe 64K 48K 0000H 3FFFH RAS 1 1A 1J 1A 1J 4000H 7FFFH RAS 2 2A 2J 2A 2J 8000H BFFFH RAS 4 3A 3J 3A 3J C000H FFFFH RAS 3 4A 4J On a revision E 64K or 48K board that does have the First Quadrant option selected th...

Page 48: ...bit A15 is not decoded The result is that both rows of RAM chips on the board and selected by two ranges of addresses as indicated in Table 5 3 Proper configuration of the Memory Address switches prevents any one memory location from responding to two different addresses Section 3 3 describes the use of these switches Table 5 3 Chip Selection HRAM 32 Address Range Row Address Strobe RAM Chip Locat...

Page 49: ...are three voltage regulators on the HRA M board These regulators produce 12 volts 5 volts and 5 volts All three of these voltages are used by the RAM chips The 5 volts is also used by the digital logic chips All three regulators are linear integrated circuits ...

Page 50: ...HRAM USER TECHNICAL MANUAL ...

Page 51: ...ACK ON UNTIL THE COVER HAS BEEN REPLACED CAUTION The electronic components on the HRAM board may be damaged by the static electricity which often builds up in the human body Before touching the memory board discharge this electricity by touching a grounded metal object such as the chassis of a Horizon which is plugged into the wall outlet Follow this procedure each time the board is handled 6 1 CH...

Page 52: ...r 2 Remove the HRAM and recheck the jumper plugs and the Memory Address switches Chapter 3 describes the use of these components 3 Reinstall the HRAM 4 Turn the power back on 5 If the HRAM configuration was changed in step 2 test the board again Otherwise proceed to Section 6 4 6 4 RUN DIAGNOSTIC PROGRAMS Load and run the RAMTEST3 or RAMTEST5 diagnostic program These programs are on the DOS 5 2 di...

Page 53: ...the spare memory board to insure that it will respond to the desired range of addresses 5 Install the spare memory board in the card cage and insert it firmly in the connector 6 Turn the power back on and test the system with the spare board installed 6 5 REPAIR PROCEDURES If it is determined that the HRAM board is defective it can be returned to any North Star Authorized Service Center for repair...

Page 54: ...HRAM USER TECHNICAL MANUAL ...

Page 55: ...2000 4000 6000 8000 A000 C000 E000 1J 1J 2J 2J 3J 3J 1H 1H 2H 2H 3H 3H 1G 1G 2G 2G 3G 3G 1F 1F 2F 2F 3F 3F 1E 1E 2E 2E 3E 3E 1D 1D 2D 2D 3D 3D 1C 1C 2C 2C 3C 3C 1B 1B 2B 2B 3B 3B HRAM 32 0000 2000 4000 6000 8000 A000 C000 E000 1J 1J 2J 2J 1J 1J 2J 2J 1H 1H 2H 2H 1H 1H 2H 2H 1G 1G 2G 2G 1G 1G 2H 2H 1F 1F 2F 2F 1F 1F 2F 2F 1E 1E 2E 2E 1E 1E 2E 2E 1D 1D 2D 2D 1D 1D 2D 2D 1C 1C 2C 2C 1C 1C 2C 2C 1B 1B...

Page 56: ...HRAM USER TECHNICAL MANUAL ...

Page 57: ...SMEMR True on memory reads SOUT True on output instructions to ports not to memory SMI True on op code fetches Cycle Status RFSH True on refresh cycles PDBIN Strobes data to the processor from memory or port Strobe PWR Strobes data from the processor to memory or port VI0 Vectored interrupt VI1 VI2 VI3 VI4 VI5 VI6 VI7 NMI Non maskable interrupt Interrupt PINT Program Interrupt chiefly for applicat...

Page 58: ...ser Technical Manual Type of Signal Signal Name Description PHASE 2 Clock from processor POC True when processor is being reset due to power on clear logic or the rear panel reset switch Miscellaneous PHANTOM Not used in a standard HORIZON ...

Page 59: ...144 2 IC 74LS156 6B 7B 16 43027 1 IC 74LS161 7F 17 43112 2 IC 74LS244 5G 8J 18 43036 2 IC 74LS258A 5H 6J 19 43040 2 IC 74LS280 5F 6F 20 43043 1 IC 74LS373 6G 21 43044 1 IC 74LS393 8H 22 43066 1 IC 75452 8A 23 43124 36 RAM CHIP 16K X 1 200NS 1A 1J 2A RECOMMENDED TYPES NATIONAL MM 5290 3 MOSTEK MK 4116 3 TI TMS 4116 20 AMD AM 9016E NEC UPD 416 2 MOTOROLA MCM 4116B 20 3A 3J 4A 4J 24 19002 1 DATA DELA...

Page 60: ...5003 1 VOLTAGE REGULATOR 791 05 VR2 40 65006 1 VOLTAGE REGULATOR 791 05 VR3 41 68006 2 SWITCH 8 POS S1 S2 42 22001 1 LED RED DE1 43 13028 36 SOCKET 16 PIN 1A 1J 2A 2J 3A 3J 4A 4J 44 13030 1 SOCKET 20 PIN 6G 45 38042 1 HEATSINK 6106 VR3 46 38043 1 HEATSINK 6107 VR2 47 38011 2 HEX NUT 6 32X1 4 AF MS 48 38018 2 SCREW MACH PH 6 32X3 8 49 38002 2 LOCKWASHER 6 50 1309303 1 HEADER DOUBLE ROW 3 PIN JP2 51...

Page 61: ...1 IC 7455132 8K 22 43144 2 IC 7455156 6B 7B 23 43027 1 IC 7455161 7F 24 43112 2 IC 74SS244 5G 8J 25 43036 2 IC 74S5258A 5H 6J 26 43040 2 IC 7455280 5F 6F 27 43043 1 IC 7455373 6G 28 43044 1 IC 74S5398 8H 29 43066 1 IC 75452 8A 30 43097 36 RAM CHIP 16K x 1 200NS IA 1J 2A 2J 3A SJ 4A 4J RECOMMENDED TYPES NATIONAL MM 5290 3 MOSTEK MK 4116 3 TI TMS 4116 20 AMD AM 9016E NEC UPD 416 2 MOTOROLA MCM 4116B...

Page 62: ... 4 CAPACITOR 47PF C4 C5 C6 C7 49 01001 61 CAPACITOR 047MF CER BY PASS 50 51 65002 1 VOLTAGE REGULATOR 7805 VR3 52 65003 1 VOLTAGE REGULATOR 7812 VR2 53 65006 1 VOLTAGE REGULATOR 79L05 VRl 54 55 68006 2 SWITCH 8 POS S1 S2 56 57 58 22001 1 DIODE ELECTRO RED DE1 59 61 61 62 63 64 65 13028 36 SOCKET 16PIN 1A 1J 2A 2J 3A 3J 4A 4J 66 67 13030 1 SOCKET 20PIN 6G 68 69 70 71 38042 1 HEATSINK 6106 VR3 72 38...

Page 63: ...DER DOUBLE ROW 3 PIN JP2 81 82 13093 04 2 HEADER DOUBLE ROW 4 PIN JP1 83 84 13093 10 1 HEADER DOUBLE ROW 10 PIN JP3 85 86 13087 8 CONN PCB MINI JUMPER JP1 3EA JP4 2EA JP2 2EA JP3 3EA 87 88 89 90 91 1309302 1 HEADER DOUBLE ROW 2 POS JP4 92 130980 2 1 HEADER SINGLE ROW 2 POS J P6 ...

Page 64: ...HRAM USER TECHNICAL MANUAL ...

Page 65: ...ES 1 Use revision A schematics with an assembly revision B board This designation is marked on the component side of the board 2 Use revision C schematics with an assembly revision E board This designation is marked on the component side of the board ...

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