Figure 172 The clocking scheme
UPP_WD2/clock frequency adjusting
No external clock is available for UPP_WD2 before VCXO starts. As reset is released, the VCXO is running and MCU
uses the 26 MHz clock while DSP is in reset. There are three identical digital phase locked loops (DPLLs); for MCU,
for DSP and for accessory interfaces, which can be controlled independently. The clock for MCU can be up to
123,5 MHz and 156 MHz is maximum clock frequency for the DSP. These clock signals are used either directly
(SDRAM IF) or divided down for the interfaces (e.g. flash IF).
RM-51
Nokia Customer Care
System module and user interface
Page 9–8
Company Confidential
9238460 (Issue 1)
Copyright ©2005 Nokia. All Rights Reserved.