WiMi300A User Manual v.1.4
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2016 NIMBUS INC. All rights reserved.
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PCI Express Interface Description
• PCI Express Interface Unit(PCIE) functions as a PCI Express legacy endpoint device that
conforms to the PCI Express Base Specification, Rev 1.1.
• As PCIe endpoint device, it can be configured to be either a master initiating PCIe operation
or a target responding to a PCIe operation. The PCIe I/F is a 2.5GHz signaling, x1 differential
link
Parameters
Description
Master transaction types
All memory transactions, except lock
Supports PCIe master DMA
IO and configuration transactions – not supported
Target transaction types
Supports two outstanding non-posted requests as a target (computer)
All memory transactions – type 0 only
Message support
Supports interrupt and error messages
Configuration space
Extended 4KB PCIe Configuration Space
Single function device
Interrupts
Support of both MSI and interrupt messages
Error reporting
Full support of PCIe baseline error reporting
Full support of advanced error reporting capability
Three error severity levels – correctable, non-fatal and fatal
Header logging and pointer to first uncorrectable error
Programmable error severity
PCI error mapping – mapping errors to PCI error reporting mechanism
Address space
Two 32-bit memory BARs
Virtual channels
Support of baseline TC0-VC0 mapping
Single VC0 HW resource
Table 5. WiMi300A PCIe Supported Features