Chapter 4
Connecting the Signals
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National Instruments Corporation
4-41
when this pin is at a logic low, and it counts up when it is at a logic high.
You can disable this input so that the application software controls the
up-down functionality and leave the DIO6 pin free for general use.
GPCTR1_SOURCE Signal
Any PFI pin can externally input the GPCTR1_SOURCE signal, which
is available as an output on the PFI3/GPCTR1_SOURCE pin.
As an input, GPCTR1_SOURCE is configured in the edge-detection mode.
You can select any PFI pin as the source for GPCTR1_SOURCE and
configure the polarity selection for either rising or falling edge.
As an output, GPCTR1_SOURCE monitors the actual clock connected
to general-purpose counter 1, even if the source clock is externally
generated by another PFI. This output is set to high-impedance at startup.
The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 23 ns high or low. There is no minimum frequency.
The 20 MHz or 100 kHz timebase normally generates GPCTR1_SOURCE
unless you select some external source.
Figure 4-36 shows the timing requirements for GPCTR1_SOURCE.
Figure 4-36.
GPCTR1_SOURCE Signal Timing
GPCTR1_GATE Signal
Any PFI pin can externally input the GPCTR1_GATE signal, which
is available as an output on the PFI4/GPCTR1_GATE pin.
As an input, GPCTR1_GATE is configured in edge-detection mode.
You can select any PFI pin as the source for GPCTR1_GATE and configure
the polarity selection for either rising or falling edge. You can use the gate
t
w
= 23 ns minimum
t
p
= 50 ns minimum
t
w
t
w
t
p
