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66
NDiS 164 User Manual
Appendix C: Watchdog Timer
CR F7h. (WDTO# Control & Status Register; Default 00h)
Bit
Read / Write
Description
7
R/W
Mouse interrupt reset watchdog timer enable
0: Watchdog timer is not affected by mouse
interrupt.
1: Watchdog timer is reset by mouse interrupt.
6
R/W
Keyboard interrupt reset watchdog timer enable
0: Watchdog timer is not affected by keyboard
interrupt.
1: Watchdog timer is reset by keyboard inter-
rupt.
5
Write “1” Only Trigger WDTO# event. This bit is self-clearing.
4
R/W
Write “0” Clear
WDTO# status bit
0: Watchdog timer is running
1: Watchdog timer issues time-out event.
3-0
R/W
These bits select IRQ resource for WDTO#. (02h
for SMI# event.)
EX.
Debug
<Enter>
- O 4E, 87
<Enter>
- O 4E, 87
<Enter>
- O 4E, 07
<Enter>
- O 4F, 08
<Enter>
- O 4E, F6
<Enter>
- O 4F, 04
(Where “04” is 1 sec. and “FF” is 255 sec.)
