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Figure 31:
Image Processing with control loop
Micro Controller Cycle Budget
Each user task is given a time budget provided by the internal micro-controller scheduler. The scheduler
will ensure the proper execution of the “host to camera” communication including execution of the
higher layer GigE Vision protocol layers first. Afterwards it gives the remaining time-slice for execution of
user defined tasks.
Figure 32:
Cycle Budget
Methodology - Adding IP to GigEPRO
First, a module has to be developed according to the following four steps for being able to add customer
image processing functionality to GigEPRO.
1.
Programming of the image processing function for the FPGA in HDL (i.e. Verilog or VHDL) and
providing i.e. the data access, the algorithm, the parameters access and the delivery of
processed data back to the FPGA base system.