N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
47
Figure 3-39 Connection between MDIO and PHY
MDIO_DATA
MDIO_CLK
ETH_RST_N
ETH_INT_N
N720 module
MDIO_DATA
MDIO_CLK
RST_N
INT_N
PHY chipset
UIM2_VCC
1.5kΩ
10kΩ
VDD_1P8
R1
R2
U1
MDIO can control one MAC or up to 32 PHY devices. It supports a maximum frequency of 2.5 MHz
and 1.8V/2.85V auto-adaption. Figure 3-40 and Figure 3-41 show MDIO input/output timing.
Figure 3-40 MDIO input timing
Figure 3-41 MDIO output timing
V
iL
(MAX)
V
iH
(MIN)
10ns MIN
10ns MIN
V
iL
(MAX)
V
iH
(MIN)
MDIO_CLK
MDIO_DATA
V
iL
(MAX)
V
iH
(MIN)
0ns MIN
300ns MAX
V
iL
(MAX)
V
iH
(MIN)
MDIO_CLK
MDIO_DATA
