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4.4 Digital Processing flow in FPGA
The
digital processing flow in FPGA is shown below.
Figure 4-4-1 FPGA Processing Block Diagram
4.5 Startup
After turning on, the camera run a startup procedure before it starts getting images
and outputting data. It takes about four seconds.
The start-up is executed by the following sequence, and as for the camera, the
preparation for the image acquisition and the output is complete when normally
ending.
(1) The camera hardware initializes. The indicator (LED green) blinks.
(2) Reads out the latest camera settings from the flash memory. (User settings if
any or factory default settings)
(3) Set up the camera with the setting value from the flash memory.
The indicator (LED green) changes from blinking into lighting.
Video Data
From Sensor
-
x
Bright image reference
multiplication
Scan Direction select
Dark image reference
subtract
x
Digital Gain
Value Set
+/-
Digital Offset
Value Set
Output Tap select &
Scan Direction select
8 or 10bit select &
Test Patter select
Flat Field Correction
Digital Gain & Offset
Exchange Pixel Order
Output Format
Video(8 or 10bit)
To Channel Link Driver
