NEC V850E/PH2, User Manual

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Chapter 15 Asynchronous Serial Interface C (UARTC)
User’s Manual U16580EE3V1UD00
15.6 Dedicated Baud Rate Generator
15.6.1 Baud rate generator configuration
The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable
counter, and generates a serial clock during transmission and reception with UARTCn. Regarding the
serial clock, a dedicated baud rate generator output can be selected for each channel.
There is an 8-bit counter for transmission and another one for reception.
Figure 15-21: Configuration of Baud Rate Generator
Remarks: 1. n = 0, 1
2. f
XX
: Internal system clock
(1) Base clock (Clock)
When the UCnPWR bit of the UCnCTL0 register is 1, the clock selected by bits UCnCKS3 to
UCnCKS0 of the UCnCTL1 register is supplied to the 8-bit counter. This clock is called the base
clock (Clock) and its frequency is called f
XCLK
. When the UCnPWR bit = 0, the clock is fixed to the
low level.
(2) Serial clock generation
A serial clock can be generated by setting the UCnCTL1 register and the UCnCTL2 register
(n = 0, 1).
The base clock is selected by UCnCKS3 to UCnCKS0 bits of the UCnCTL1 register.
The frequency division value for the 8-bit counter can be set using bits UCnBRS7 to UCnBRS0 of
the UCnCTL2 register.
Clock
(f )
XCLK
Selector
UCnPWR
8-bit counter
Match detector Baud rate
UCnCTL2:
UCnBRS7 to UCnBRS0
1/2
UCnPWR, UCnTXEn (or UCnRXE)
UCnCTL1:
UCnCKS3 to UCnCKS0
f /4
XX
f /8
XX
f /16
XX
f /32
XX
f /64
XX
f /128
XX
f /256
XX
f /512
XX
f /1024
XX
f /2048
XX
f /8192
XX
f /2
XX