NEC V850E/PH2, User Manual

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Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10)
User’s Manual U16580EE3V1UD00
(1) Timer ENC10 (TMENC10)
TMENC10 is a 2-phase encoder input up/down counter and general-purpose timer.
It can be read/written in 16-bit units.
Reset input clears TMENC10 to 0000H.
Cautions: 1. Write to TMENC10 is enabled only when the TM1CE bit of the TMC10 register is
“0” (count operation disabled).
2. It is prohibited to clear the CMD bit (general-purpose timer mode) to 0 and to set
the MSEL bit (UDC mode B) of the TUM register to 1.
3. Continuous reading of TMENC10 is prohibited. If TMENC10 is continuously read,
the second value read may differ from the actual value. If TMENC1n must be read
twice, be sure to read another register between the first and the second read
operation.
4. Writing the same value to the TMENC10, CC100, and CC101 registers, and the
STATUS10 register is prohibited.
Writing the same value to the CCR10, TUM10, TMC10, SESA10, and PRM10
registers, and CM100 and CM101 registers is permitted (writing the same value is
guaranteed even during a count operation).
Figure 12-2: Timer ENC10 (TMENC10)
TMENC10 start and stop is controlled by the TM1CE bit of timer control register 10 (TMC10).
The TMENC10 operation consists of the following two modes.
(a) General-purpose timer mode
In the general-purpose timer mode, TMENC10 operates as a 16-bit interval timer, free-running
timer, or for PWM output.
Counting is performed based on the clock selected by software.
Division by the prescaler can be selected for the count clock from among f
XX
/8, f
XX
/16, f
XX
/32,
f
XX
/64, f
XX
/128, f
XX
/256, or f
XX
/512 with bits PRM102 to PRM100 of prescaler mode register 10
(PRM10) (f
XX
: internal system clock).
(b) Up/down counter mode (UDC mode)
In the UDC mode, TMENC10 functions as a 16-bit up/down counter, counting based on the
TCUD1 and TIUD1 input signals.
Two operation modes can be set with the MSEL bit of the TUM register for this mode.
• UDC mode A (when CMD bit = 1, MSEL bit = 0)
TMENC10 can be cleared by setting the CLR1 and CLR0 bits of the TMC10 register.
• UDC mode B (when CMD bit = 1, MSEL bit = 1)
TMENC10 is cleared upon match with CM100 during TMENC10 up count operation.
TMENC10 is cleared upon match with CM101 during TMENC10 down count operation.
After reset: 0000H R/W Address: FFFFF6B0H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMENC10