NEC V850E/CA1 ATOMIC, Preliminary User'S Manual

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Chapter 6 DMA Functions (DMA Controller)
Preliminary User’s Manual U14913EE1V0UM00
6.5 Transfer Mode
6.5.1 Single transfer mode
In single transfer mode, the DMAC releases the bus at each byte/halfword/word transfer. If there is a
subsequent DMA transfer request, transfer is performed again once. This operation continues until a
terminal count occurs.
When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the
higher priority DMA request always takes precedence.
6.5.2 Single-step transfer mode
In single-step transfer mode, the DMAC releases the bus at each byte/halfword/word transfer. Once a
DMA transfer request signal is received, transfer is performed again. This operation continues until a
terminal count occurs.
When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the
higher priority DMA request always takes precedence.
6.5.3 Block transfer mode
In the block transfer mode, once transfer starts, the DMAC continues the transfer operation without
releasing the bus until a terminal count occurs. No other DMA requests are acknowledged during block
transfer.
After the block transfer ends and the DMAC releases the bus, another DMA transfer can be acknowl-
edged.
6.6 Transfer Types
6.6.1 Two-cycle transfer
In two-cycle transfer, data transfer is performed in two cycles, a read cycle (source to DMAC) and a
write cycle (DMAC to destination).
In the first cycle, the source address is output and reading is performed from the source to the DMAC.
In the second cycle, the destination address is output and writing is performed from the DMAC to the
destination.