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CHAPTER 4 INTERFACES

PRELIMINARY

NEC confidential and Proprietary

158

(5) Clearing the detailed cause register

The set bits of the detailed cause registers are cleared by CPU access. These bits may be cleared by reading or

writing. Whether to clear by reading or writing can be specified for each bit. Each detailed cause register has

three addresses: read clear, write clear, and read clear enable.

(a) Read clear

To clear a bit once it has been read, write 1 to the corresponding bit position at the read clear enable

address. When the read clear address is read, only the bit for which 1 has been written to the corresponding

bit position at the read clear enable address is cleared to 0. The bit that is disabled from being cleared by

the read clear enable register is not cleared. In default mode, all the bits can be cleared once they have

been read.

(b) Read only / Write clear

After reading the contents of a register, write 1 to the bit position in the register corresponding to the bit to be

cleared. When write 0 to the register, the content of register is not clear.

Figure 4-29. Detailed Cause Register Clearing Method

Read clear enable register

Mask register

Read clear address

Read only / Write clear address

Detailed cause register

Setting

Clear

Contents display

Table 4-12. Functions of the Interrupt Cause Registers

Access Destination

Description

Read clear address

This address is used for reading the contents of the register and then for

clearing the register. Note that only those bits enabled in the read clear

enable register are cleared to 0. Any attempt to perform write access to this

address is ignored.

Read only / Write clear address

This address is used to read the contents of the register and used to write-

clear the contents of the register.

Write the address so that 1 written over the bit to be write-cleared.

Read clear enable register

This register is used to enable or disable the read clear operation on a per-

bit basis. Only those bits set to 1 in this register are cleared to 0 when read

access to the read clear address is performed. By default, all the bits are

set to 1 (enable).

Mask register

This register is used to mask or unmask each interrupt cause. Masking the

detailed cause register masks reflection on the PICR register, and masking

of the PICR register masks asserting the interrupt signal active. By default,

all the bits are set to 1, meaning that all the interrupt causes are masked.

Summary of Contents for UPD98413

Page 1: ...µPD98413 NEASCOT P65 QUAD 622M ATM POS SONET FRAMER Preliminary User s Manual rev0 1 Document No 2SYSM FAD 0166 Date Published September 2001 CP K NEC Corporation ...

Page 2: ...r other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or of others Descriptions of circuits software and other related information in this document a...

Page 3: ...NEC confidential and Proprietary 3 SUMMARY OF CONTENTS CHAPTER 1 GENERAL 9 CHAPTER 2 PIN FUNCTION 17 CHAPTER 3 FUNCTIONAL OUTLINE 39 CHAPTER 4 INTERFACES 113 CHAPTER 5 REGISTERS 159 CHAPTER 6 JTAG BOUNDARY SCAN 305 ...

Page 4: ...PRELIMINARY NEC confidential and Proprietary 4 MEMO ...

Page 5: ...n 32 2 2 11 Power and Grounding Pins 32 2 2 12 Others 32 2 2 13 Handling Unused Pins 33 2 2 14 Initial States of Each Pin 34 CHAPTER 3 FUNCTIONAL OUTLINE 37 3 1 SONET Overhead Processing 41 3 1 1 Transmission Function 41 3 1 2 Reception Function 47 3 2 ATM Function 59 3 2 1 Transmit ATM function 60 3 2 2 Receive ATM function 62 3 3 POS FUNCTIONS 66 3 3 1 Transmission POS functions 67 3 3 2 Recepti...

Page 6: ... POS Interface Error Detection 138 4 4 Overhead Insert Extract Interfaces and Section Line DCC Insert Extract Interface 140 4 4 1 OH Insert Interface 141 4 4 2 OH Extract Interfaces 144 4 4 3 Transmit Section and Line DCC Insert Interface 145 4 4 4 Receive Section and Line DCC Extract Interface 145 4 5 Frame Pulse input pins 146 4 6 General Purpose Input and Output Ports 147 4 7 Alarm Insertion De...

Page 7: ...TAG Data Input Pin 308 6 3 4 JDO JTAG Data Output Pin 308 6 3 5 JRST_B JTAG Reset Pin 308 6 4 Operation Description 309 6 4 1 TAP Controller 309 6 4 2 TAP Controller State 309 6 5 TAP Controller Operation 314 6 6 Initializing TAP Controller 317 6 7 Instruction Register 317 6 7 1 BYPASS Instruction 318 6 7 2 EXTEST Instruction 318 6 7 3 SAMPLE PRELOAD Instruction 318 6 7 4 Boundary Scan Data Bit De...

Page 8: ...PRELIMINARY 8 MEMO ...

Page 9: ...line interface Integrated SERDES Clock data recovery and Clock synthesis Provides loopback functions line and equipment loopback 1024 byte FIFO for each transmit and receive FIFO Provides IEEE 1149 1 JTAG testing Industrial temperature range 40 to 85 576 BGA package and 2 5V power supply SONET Detects LOS OOF LOF Line AIS Line RDI LOP Path AIS Path RDI Enhanced and One bit Path PLM and Path UNEQ I...

Page 10: ...h RFC 2615 1619 and 1662 Inserts flag sequence between each POS packet Provides packet delineation from SONET SDH payload by detection flag sequence Byte stuffing and destuffing Generates and checks 32 16 bit FCS Data scrambling and descrambling Inserts address and control fields and detects address and control error Detects minimum and maximum size packet errors Provides performance counters Tran...

Page 11: ...rs ATM switches Access concentrators Add drop multiplexers and Digital cross connects Typical Application P65 Optical Transceiver Serial 622MHz PECL ATM POS Device UTOPIA L3 POS PHY L3 MPU Control 32 bit LVTTL Optical Transceiver Optical Transceiver Optical Transceiver 32 bit 104MHz LVTTL ...

Page 12: ...9 44M RTOHFP RPOHFP ROHD 2 ROHAV PIO 8 Alarm Detection RCS 19M TCS 19M Rx ATM Processor Rx POS Processor Payload Type Selector Clock Recovery Tx FIFO Control Tx FIFO Tx POS Processor Tx ATM Processor Tx POH Processor Frame Gen BIP Tx SOH Processor BIP Clock Synthesizer ATM POS Interface Rx SOH Processor Rx POH Processor Frame Sync BIP OAM Pointer Control BIP Overhead Insertion Block REFCLK Trancei...

Page 13: ... TLDCLK0 3 TPOHFP0 3 PIO 7 0 JCK JMS JDI JRST_B JDO Receive Alarm Pins RALMA0 3 RALMC0 3 RALMB0 3 Overhead Insert Extract Interface Power and Ground VDD GND INT_B Transmit Alarm Pins IC Others RVAL RSX TEOP TMOD 1 0 TERR TSX STPA TXADDR 1 0 TADR 1 0 RXADDR 1 0 TDOT0 3 TDOC0 3 RXCLAV1 RMOD1 RXCLAV2 REOP RXCLAV3 RERR TXCLAV1 DTPA1 TXCLAV2 DTPA2 TXCLAV3 DTPA3 TALMA0 3 TALMC0 3 TALMB0 3 8 Section line...

Page 14: ...RFC 1662 PPP in HDLC like framing July 1994 ITU Recommendation G 707 Network Node Interface For The Synchronous Digital Hierarchy 1996 ITU Recommendation G 783 Characteristics of Synchronous Digital Hierarchy SDH Equipment Functional Blocks 1996 ITU Recommendation I 432 ISDN User Network Interfaces March 93 ANSI T1 105 Synchronous Optical Network SONET Basic Description including Multiplex Structu...

Page 15: ...PRELIMINARY NEC confidential and Proprietary 15 CHAPTER 2 PIN FUNCTION 2 1 Pin Configuration TBD ...

Page 16: ...CHAPTER 2 PIN FUNCTION PRELIMINARY NEC confidential and Proprietary 16 Pin Arrangement Table TBD ...

Page 17: ...reference clock for both the CDR and the synthesizer PLL circuits RFCKPLT must be connected to a logic one and RFCKPLC to a logic zero state when RFCKTTL is used RFCKTTL I LVTTL TTL reference clock input TTL reference clock inputs for both the CDR and the TxPLL circuits RFCKTTL must be tied high if RFCKPLT RFCKLC is used LPFP Analog Loop Filter Capacitor for synthesizer PLL The TxPLL loop filter c...

Page 18: ...ceive signal power from the Optical module and it is active high Each port has one pin CD0 corresponds to PORT0 while CD3 corresponds to PORT3 CDVREF I 3 3V PECL This pin input reference potentials intermediate potentials for single ended PECL input signals CD0 3 LPFC0 LPFC3 Analog Loop Filter Capacitor the CDR The CDR loop filter capacitor is connected to this pin Each port has one pin LPFCGND0 L...

Page 19: ... RXENB_B at the rising edge of RXCLK When it detects the low level of RXENB_B it updates the output of RSOC and RXDATA starting from the next clock cycle and then transfers the receive cell data If RXENB_B is high the µPD98413 stops the output of RSOC and RXDATA starting from the next clock cycle RXPRTY O LVTTL Receive data path parity This pin generates an odd parity bit for the output data on RX...

Page 20: ...a on TXSOC and TXDATA to the transmit FIFO at the edge of TXCLK If TXENB_B is high the data on TXSOC and TXDATA is not loaded to the transmit FIFO TXCLAV0 3 O LVTTL Transmit cell buffer available This signal posts notification of the vacancy of the transmit FIFO to the ATM device If the number of cells stored in the transmit FIFO has reached the threshold value set by the APHIGH 7 0 bits of the FT...

Page 21: ...ice to request a transfer interrupts When RENB_B is low the µPD98413 updates the RDAT RMOD RSOP REOP RERR RPRTY RVAL and RSX signals at the next clock pulse When RENB_B is high the µPD98413 will remain unchanged the RDAT RMOD RSOP REOP RERR RPRTY RVAL and RSX signals at the next clock pulse RPRTY O LVTTL Receive bus parity When receive packet data is to be output from RDAT odd or even parity data ...

Page 22: ...PD98413 causes RERR to go high RERR and REOP must be asserted at the same time RVAL O LVTTL Receive data valid signal Indicates whether the receive data RDAT and other signals are valid When RVAL is high the RDAT RMOD RSOP REOP RERR and RPRTY signals are valid RSX is valid when RVAL is low RSX O LVTTL Receive start of transfer Signal for controlling the port address specification using RDAT 7 0 at...

Page 23: ...TPRTY signals are valid TSX is valid when TENB_B is high TPRTY I LVTTL Transmit bus parity Signal for inputting the odd or even parity for the data to be input to TDAT Upon detecting a parity error the uPD98413 reports it with an interrupt Even if a parity error is detected data transfer continues without being affected TEOP I LVTTL Transmit end of packet Signal indicating the end position of a tr...

Page 24: ...tary 24 TSX I LVTTL Transmit start of transfer Signal for controlling the port address specification using TDAT 7 0 at the start of transfer When TSX is high and TENB_B is high the port used to start transfer can be selected with the port address input to TDAT 7 0 ...

Page 25: ...d is capable of data transfer When low STPA indicates that the transmission FIFO is full or almost full and is not capable of data transfer The high low transition of STPA transmission FIFO status is programmable PTPA O LVTTL Polled port transmit packet available In status polling signal indicating the status of the polled port It indicates the status of the port selected by TADR When high PTPA in...

Page 26: ...1 to AD0 bus is a 32 bit bi directional multiplexed address data bus During the first clock of a transaction AD31 to AD0 contains a physical byte address During subsequent clocks AD31 to AD0 contains data When the µPD98413 is not accessing the bus it places the AD bus in the high impedance state CS_B I LVTTL I O chip select signal When this signal is low access to the internal registers of the µPD...

Page 27: ...puts of transmit TOH data is started TPOHFP0 3 O LVTTL Transmit POH frame pulse output This signal is driven high 2 clock cycle before the inputs of transmit POH data is started TOHD 1 0 0 3 I LVTTL Transmit TOH POH data input 2 bit bus This is a 2 bit data bus that inputs transmit TOH POH data It inputs the TOH POH data on TOHD as 1 byte in 4 clock cycles starting to data input from 2 clock cycle...

Page 28: ...ut of the receive TOH data is started RPOHFP0 3 O LVTTL Receive POH frame pulse output This signal goes high coincident with the clock cycle in which output of receive POH data is started ROHD 1 0 0 3 O LVTTL Receive TOH POH data output 2 bit bus This 2 bit bus outputs receive TOH POH data It starts output of the receive TOH POH onto ROHD starting from the clock cycle at the same time RTOHFP is ou...

Page 29: ...ransmit line DCC TKD signals contains the serial line data communications channel D4 D12 TLD0 corresponds to PORT0 while TLD3 corresponds to PORT3 RSDCLK0 3 O LVTTL Receive section DCC clock RSDCLK This pin outputs a 216kHz clock RSDCLK0 corresponds to PORT0 while RSDCLK 3 corresponds to PORT3 RSD0 3 O LVTTL Receive section DCC RSD signal contains the serial section data communications channel D1 ...

Page 30: ...ress No I O Function PIO 7 0 I O LVTTL General purpose input output port These are general purpose input or output pins that input or output the state signals of external peripheral devices It is possible to change to input or output with the MDDGEN register GPIOM 7 0 bit setting General purpose input The signal levels of these pins are reflected on the bits of the internal GPIN register Changes i...

Page 31: ...indicated is selected by setting the internal RALMR registers TALMC 0 3 TALMB 0 3 TALMA 0 3 I LVTTL Alarm signal input The alarm which it is possible to insertion is LAIS PAIS LRDI PRDI PERDI Payload defect Server defect Connectivity defect and the following code corresponds to TALMCx TALMAx 000 No Alarm 001 LAIS 010 PAIS 011 LRDI 100 One bit PRDI mode PRDI one bit PRDI G1 bit5 1 Enhanced PRDI mod...

Page 32: ... Pin Name Serial No Address No I O Level Function RESET_B I LVTTL Reset signal The RESET_B signal provides a means of initializing the µPD98413 i e at power on After the completion of a reset the µPD98413 can start normal operation Once RESET_B has been set to low it resets the µPD98413 internal state machines and registers and forces all 3 state signals to the high impedance state Reset input is ...

Page 33: ...CHAPTER 2 PIN FUNCTION PRELIMINARY NEC confidential and Proprietary 33 2 2 13 Handling Unused Pins TBD ...

Page 34: ...CHAPTER 2 PIN FUNCTION PRELIMINARY NEC confidential and Proprietary 34 2 2 14 Initial States of Each Pin TBD ...

Page 35: ...PRELIMINARY NEC confidential and Proprietary 35 MEMO ...

Page 36: ...iption 2 D31 to D0 bits This description is mainly used to indicate the bits in an internal register of the µPD98413 The bits correspond to the AD31 to AD0 pins of the external CPU interface 1 Indicating bits in overhead byte Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 1 2 3 4 5 D31 D23 D15 D7 D30 D22 D14 D6 D29 D21 D13 D5 D28 D20 D12 D4 D27 D19 D11 D3 D26 D18 D10 D2 D25 D17 D9 D1 D24 D16 D8 D...

Page 37: ...sued to the µPD98413 and its status registers are polled via the management interface Figure 3 1 µ µ µ µPD98413 and Peripheral Blocks OSC 77 76 or 19 44 MHz ATM POS switch element µPD98413 NEASCOT P65 UTOPIA POS interface Alarm Management interface Fiber Transceiver UTP Transceiver Port 0 Transceiver Receiver Line interface Management element Line interface card Switch control module Port 1 Transc...

Page 38: ...ine overhead LOH Direction of transmission STS 12c SPE 1 043 bytes Transport overhead TOH 36 bytes 3 6 Path overhead POH 1 byte ATM cell POS packet J0 G1 C2 H3 F1 J1 K2 Z0 B2 H1 B1 A1 A1 A1 A2 H2 H1 H1 B2 B2 H4 B3 F2 Z4 Z3 Z5 S1 D10 D7 D4 D1 D12 E2 D9 D6 D3 Z2 Z1 Z1 Z2 A2 H2 A2 H2 Z2 M1 H3 H3 K1 D11 D8 D5 E1 D2 Z0 1 080 bytes 1 044 bytes 12 bytes 12 bytes 12 bytes Payload Fixed Stuff 3byte Fixed s...

Page 39: ...changed by the external insert interface of the OH byte Unused byte area Default value is 00H Can be changed by the external insert interface of the OH byte A1 A2 Frame synchronization B2 Line BIP 96 J1 STS path trace J0 Section trace K1 K2 APS channel B3 Path BIP 8 Z0 Section growth C2 STS path signal label B1 Section BIP 8 D4 D12 Line data communication channel G1 Path status E1 Order wire S1 Sy...

Page 40: ...ure 3 4 Figure 3 4 STS 12c SPE 1 2 3 4 5 6 7 8 9 STS POH 9 bytes 1 044 bytes Fixed stuff bytes 27 bytes 1 STS TOH 324 bytes 36 bytes STS 12c Payload 9 360 bytes STS 12c SPE Synchronous Payload Envelope 3 The overhead generated by the µPD98413 and the selection of a mode is described below a Selecting contents of unused OH byte All 00H is inserted into the following areas of TOH hatched area in Fig...

Page 41: ... Z0 byte of 11 These values can be changed to AAH from the 4th byte to the 11th byte of the Z0 byte by using the Z0M bit of the MDSOHT register Figure 3 6 Inserted Value of Z0 Byte J0 0 Z0 1 Z0 2 Z0 3 Z0 4 Z0 5 Z0 6 Z0 7 Z0 8 Z0 9 Z0 10 Z0 11 Default 01 02 03 04 05 06 07 08 09 0A 0B 0C AA mode 01 02 03 04 AA AA AA AA AA AA AA AA d Pointer generation The pointer on the fourth line of TOH consists o...

Page 42: ...ts Frequency Justification operation I Increment bit Requests Positive Justification operation D Decrement bit Requests Negative Justification operation Concatenation indication Indicates concatenation Contents of H1 through H3 Bytes Transmitted by µ µ µ µPD98413 H1 Byte H2 Byte H3 Byte 1st byte 0110 SS10 0000 1010 0000 0000 2nd and onward 1001 SS11 1111 1111 0000 0000 Remark The pointer value is ...

Page 43: ...the transmission destination device If a B2 error is detected in a receive frame the number of errors is stored into M1 byte of line overhead as Line REI Remote Error Indication for transmission If a B3 error is detected the number of errors is stored into G1 bits 1 to 4 as Path REI for transmission 2 Insert function of transmit OH byte The µPD98413 supplies the following four types of means to se...

Page 44: ...tes can be input at some timing but even if they are input data cannot be changed to these bytes because the µPD98413 internally overwrites these bytes for output c Section and Line DCC insert interface The µPD98413 has an input interface that is used to set the contents of the Section and Line DCC from a peripheral device D1 through D3 bytes can be inserted from the Section DCC insert interface a...

Page 45: ...ed depending on the status of the reception side Automatic transmission can also be masked by setting the ALRDIM bit of the MDLOHT register Line RDI and the APRDIM bit of the MDPOHT register Path RDI For details of transmitting an alarm see Section 3 4 1 6 Transmitting a pseudo frame generating error A pseudo frame that causes the opposing receiver unit to detect an error is available for testing ...

Page 46: ...e patterns other than the above synchronization pattern are detected the µPD98413 enters the frame non synchronization Out of Frame status The number of frames required by the µPD98413 to enter the In frame status number of backward protection stages δ and the number of frames required by the µPD98413 to enter the Out of Frame status number of forward protection stages α can be changed by using th...

Page 47: ...PD98413 is able to select the LOS termination condition Bellcore mode or ANSI mode by the LOST bit of the MDSOHR register Bellcore Mode If the incoming signal has two consecutive valid framing alignment patterns and no pulse free intervals for 25µ s consecutive time between that tow consecutive valid framing ANSI Mode If the incoming signal that have no pulse free intervals of 25 µ s for 125µ s If...

Page 48: ... enable or disable changing of the pointer value NDF Enable Requests changing of the pointer value If three bits or more of the four bits coincide with 1001 1001 1000 1011 1101 0001 NDF Disable Does not request changing of the pointer value If three bits or more of the four bits coincide with 0110 0010 0110 0100 0111 1110 SS bit Indicate the type of SPE Pointer Indicates the position of first byte...

Page 49: ... Bellcere mode and ITU T mode In the Bellcore mode H1 1 and H2 1 H1 2 and H2 2 to H1 12 and H2 12 is processed one sequencer and the overall status is decided this one sequencer In the ITU T mode H1 1 and H2 1 H1 2 and H2 2 to H1 12 and H2 12 is processed each sequencer total 12 sequencer and the overall status is decided these sequencer However by setting the ITUM bit of the MDPTRR register the s...

Page 50: ... can be specified by using the SSM bit of the MDPTRR register and the expected value to be verified can be set by using the SSR 1 0 bits of the MDPTRR register In the default mode the SS bit are not checked 2 In the default mode the condition of incr_ind indication is Three or more I bits are inverted and three or more D bits are not inverted and decr_ind indication is Three or more I bits are inv...

Page 51: ... H1 2 and H2 2 to H1 12 and H2 12 The indication shown in Table 3 5 is interpreted depending on the NDF SS bits and pointer value extracted from the H1 2 and H2 2 to H1 12 and H2 12 bytes Table 3 5 Concatenation Interpretation Indication NDF SS Bits Pointer 1 conc_ind Enable Don t Care All 1 2 AIS_ind 1111 11 All 1 3 inv_point Cases other than above Table 3 6 Concatenation Interpretation History I...

Page 52: ...o H1 12 and H2 12 is processed one sequencer and the overall status is decided this one sequencer Table 3 7 shows the status transition condition of pointer processing of H1 1 and H2 1 H1 2 and H2 2 to H1 12 and H2 12 Figure 3 11 shows the status transition Figure 3 11 Status Transition of Processing Bellcore MODE LOP AIS 3 3 3 3 6 6 6 6 NORM 9 8 7 2 5 4 5 4 1 ...

Page 53: ...f all H1 2 and H2 2 to H1 12 and H2 12 Concatenation Interpretation is included in the status transition but can be excepted by the AIST1 bit of the MDPTRR register setting 3 In the default mode reception of conc_ind of all H1 2 and H2 2 to H1 12 and H2 12 Concatenation Interpretation is included in the status transition but can be excepted by the AIST2 bit of the MDPTRR register setting 4 In the ...

Page 54: ... and H2 2 to H1 12 and H2 12 And Figure 3 13 shows the overall status transition Pointer indication processing H1 1 and H2 1 are independently checked in a pair of H1 1 and H2 1 The Pointer indication processing is same as the Bellcore mode Note In the ITU T mode some option mode must be configured by the MDPTRR register The configuration is as follow Bit Setting LOPT Set to 1 AIST1 Set to 1 AIST2...

Page 55: ...ISCT bit of the MDPTRR register Overall indication processing The overall status of the pointer changes depending on the status transition caused by the pointer processing of H1 1 and H2 1 and on the status transition of each pointer caused by the concatenation indication processing of H1 2 and H2 2 to H1 12 and H2 12 Figure 3 13 Overall Pointer Status Transition NORM LOP AIS c b b a a d Table 3 9...

Page 56: ...ived the indication is Inv_point This condition can be invalidated by using the FJM1 bit of the MDPTRR register incr_ind Positive Justification If it is detected that three or more I bits and up to two D bits of a new pointer are inverted with NDF Disable the byte at pointer address 0 is not received as payload data decr_ind Negative Justification If it is detected that up to two I bits and three ...

Page 57: ...nterface The µPD98413 has an output interface through which a peripheral device can obtain the contents of the Section and Line DCC as signals D1 through D3 bytes can be extracted via the Section DCC extract interface and D4 through D12 bytes can be extracted via the Line DCC extract interface see Section 4 4 d Reception of J0 and J1 trace messages The µPD98413 stores a 16 or 64 byte trace message...

Page 58: ...tains a GFC field 4 bits In the case of the network node interface NNI however the corresponding field is defined as a VPI field that is 12 bits long Figure 3 15 Structure of ATM Cell User network interface UNI Network node interface NNI CLP 8 7 6 5 4 3 2 1 HEC VCI PTI GFC VPI VPI Payload data 48 bytes Transmission sequence CLP 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 53 HEC VCI PTI VPI Header Payload...

Page 59: ...s been deasserted Detection of transmit FIFO overflow error When a transmit FIFO is full and µPD98413 receives next cell µPD98413 indicates the detection of a transmit FIFO overflow error The received cell data is ignored and not stored to the transmit FIFO after transmit FIFO overflow occurs If the transmit FIFO has a vacancy the detection of the overflow is cleared Parity check At the transmissi...

Page 60: ...ure3 16 shows the formats of the idle cell and unassigned cell generated by the µPD98413 Figure 3 16 Format of Vacant Cell Inserted by µ µ µ µPD98413 1 2 3 4 5 1 2 47 48 Idle cell 00H 00H 00H 01H 52H 6AH 6AH 6AH 6AH Unassigned cell 00H 00H 00H 00H 55H 00H 00H 00H 00H d Scramble of ATM cell The data of an ATM cell is scrambled by using the following polynomial The range of scramble is limited to th...

Page 61: ...is identified by checking CRC calculation of a bit string accommodated in the SPE payload area shifting the bit string one byte at a time to check the point at which the syndrome becomes 0 The following polynomial expression is used for this purpose G X X 8 X 2 X 1 Figure shows the status transition of cell synchronization by means of header error control Figure 3 17 Cell Synchronization Status Tr...

Page 62: ...er of backward protection stages δ are α 7 and δ 6 in the default mode However α can be changed by setting the OCDD 1 0 bits of the MDATMR register and δ can be changed by setting the OCDT 1 0 bits Table 3 9 Number of Forward Backward Protection Stages of Cell Synchronization Number of Forward Protection Stages α MDATMR Register OCDD 1 0 Number of Backward Protection Stages δ MDATMR Register OCDT ...

Page 63: ...ror detection Cell dropped Cell synchronization status SYNC From cell synchronization status to hunting status From preceding synchronization status to cell synchronization status Detection mode Correction mode Cell is dropped without correcting error An error of only one bit is corrected in the correction mode and then the detection mode is set HEC errors are continuously monitored in the correct...

Page 64: ... DCHP register so that an unassigned cell can be dropped or passed along with the idle cell In the default only CLP bit of the COMP field is set to 1 therefore only idol cell is dropped Unassigned cell is not dropped Figure 3 19 DCHP Register 15 8 7 0 GFC3 GFC2 GFC1 GFC0 PTI2 PTI1 PTI0 CLP GFC3 GFC2 GFC1 GFC0 PTI2 PTI1 PTI0 CLP DCHP Register Setting Examples COMP Field CLP Bit MASK Field CLP Bit C...

Page 65: ...OS interface and maps it as POS packets into a SONET payload inserting a flag sequence 7Eh between packets On the receiving end the µPD98413 extracts POS packets from the SONET frame payload entered from the line interface based on the flag sequence 7Eh It then performs HDLC processing on the POS packets and sends them to the POS interface The mapping of POS packets into a SONET payload and the PO...

Page 66: ...control byte generation function is optional and it may be disabled by the ADRM bit of the MDPOST register b FCS generation The µPD98413 executes an FCS operation CRC 32 or CRC CCIT operation on the entire packet data and adds an FCS field to the end of the POS packet The user can select between a 32 bit FCS and a 16 bit FCS for the FCS field to be added by the µPD98413 And user can selects the FC...

Page 67: ...ed with 0x20 EXORed with 0x20 Original data Stuffed data Inserts 0x7D d Data scrambling The µPD98413 scrambles the entire SONET payload including the POS packets and flag sequences excepted POH and Fixed stuff The polynomial used for scrambling is as follows g x 1 x 43 The scrambling function is optional and it may be disabled by the PSCM bit of the MDPOST register e SONET overhead byte for POS In...

Page 68: ...IFO overflow occurs the remaining data for that packet is entered the data is entered without TSOP being asserted the µPD98413 discards that data Transmission FIFO underflow If a transmission FIFO underflow occurs during packet transmission the transmission FIFO becomes empty before TEOP is asserted the µPD98413 inserts 7Dh and 7Eh after the data sent before the underflow occurs and sends the data...

Page 69: ...ments the transmit valid packet counter This counter is selectable in units of packets or bytes by the VPCTM bit of the MDCNTT register Transmit abort packet counter Upon sending an abort packet the µPD98413 increments the send abort packet counter This counter includes the counts of the abort packet due to a transmit FIFO underflow and TERR is asserted See the description above for details of the...

Page 70: ...that data is insert as the next partial packet In default this mode is disabled It is enabled by the HALTM bit of the MOPOST register Figure 3 24 Packet insert on HALT mode Transmit Address Control Partial packet 7Eh FCS 7Dh xxh 7Eh 7Eh Partial packet 7Eh 7Eh partial packet 7Dh xxh Flag sequence Address Control Partial packet FCS Inserting Packet Flag sequence Flag sequence Flag sequence Terminal ...

Page 71: ...ontaining the POS packets and flag sequences The polynomial used for descrambling is as follows g x 1 x 43 The descrambling function is optional and it may be disabled by the PSCM bit of the MDPOSR register b Byte destuffing The µPD98413 supports the byte destuffing function Upon detecting a 7Dh control escape byte in a POS packet the byte destuffing of the µPD98413 deletes that byte and EXORs the...

Page 72: ...you to set the minimum receive packet size in the PRENR1 register If receiving a packet whose size is below the minimum the µPD98413 increments the short size packet counter and indicates it by the interrupt If receiving such a short size packet the µPD98413 outputs it as an error packet from the POS interface At the end of the packet the RERR pin is asserted for notification The Short packet size...

Page 73: ... MDPOSR register g Performance monitors The µPD98413 supports the following receive error handling and performance counters Each counter is described below All the counters are 32 bit counters Receive valid packet counter Receive abort packet counter Receive Address error counter Receive FCS error counter Receive FIFO overflow counter Receive short size packet counter Receive long size packet coun...

Page 74: ...ea settable in an appropriate register programmable is reserved in the reception FIFO Any new packet that otherwise would be received during the suspended reception is discarded internally as in the case where a reception FIFO overflow occurs at the beginning of a packet In this case too the reception FIFO overflow counter is incremented Short size packet counter The µPD98413 allows you to set the...

Page 75: ...e packet extract is paused Then if expect data except 7E that data is recognized as the next partial packet Figure 3 26 Packet Extracting on HALT mode Address Control Partial packet 7Eh FCS 7Dh xxh 7Eh 7Eh Partial packet 7Eh 7Eh partial packet 7Dh xxh Flag sequence Address Control Partial packet FCS Extructing Packet Flag sequence Flag sequence Flag sequence Terminal of Partial paket Terminal of P...

Page 76: ...ster 2 Input a signal to the TALM pins All the H1 H2 and H3 bytes and all the bits in the SPE area before frame scramble are set to 1 4 Line RDI 1 Sets the LRDI bits of the CMALM register 2 Input a signal to the TALM pins 3 Automatic transmission due to occurrence of an internal cause Bits 6 to 8 of the K2 byte of the OH byte are 110 5 Path RDI 1 Sets the PRDI bits of the CMALM register 2 Input a ...

Page 77: ... AIS Line Alarm Indication Signal Line AIS is a line alarm indication signal that detects a failure in the upstream and sends an alarm to the downstream during relaying Transmitting Terminating method The Line AIS frame can be transmitted in the following two ways The frame is transmitted or terminated by observing the boundary of the frame 1 Set the LAIS bit of the CMALM register to 1 While this ...

Page 78: ...gnal that reports detection of a path receive failure to a unit in the upstream µPD98413 supports two modes of One bit RDI and Enhanced RDI This mode can be selected by the PRDIM bit of the MDPOHT register One bit Path RDI Transmitting Terminating method The One bit Path RDI frame can be transmitted in the following three ways The frame is transmitted or cleared by observing the boundary of the fr...

Page 79: ...n be disabled by using the APRDIM bit of the MDPOHT register LCD is not included in the condition of automatic transmission of ERDI P Payload defect in the default mode but can be included in the condition by using the LCDO bit of the MDPOHT register LCD also is invalid in the POS mode Path TIM is not included in the condition of automatic transmission of ERDI P Connectivity defect in the default ...

Page 80: ... the external peripheral device Table 3 14 Alarms and Failures 1 4 LOS Loss Of Signal Receive signal lost status Detection See section 3 1 2 Table 3 2 Termination See section 3 1 2 Table 3 2 OOF Out Of Frame Frame non synchronization Detection If a frame synchronization pattern cannot be detected α times in a row at the positions of the A1 and A2 bytes Termination If a frame synchronization patter...

Page 81: ...te reception failure information Indicates detection of line reception failure LOS LOF or Line AIS in unit of transmission destination downstream Detection If frames with K2 byte bits 6 to 8 being 110 are received n times continuously Termination If frames with K2 byte bits 6 to 8 being other than 110 are received n times continuously n 3 or 5 This can be selected by using the LRDIDT bit of the MD...

Page 82: ...t 101 100 and 111 ERDI P Server defect 110 ERDI P Connectivity defect Termination If frames with bit 5 to 7 of G1 byte being the following values are received n times continuously ERDI P Payload termination The values other than 010 ERDI P Server termination The values other than 101 100 and 111 ERDI P Connectivity termination The values other than 110 n 3 5 or 10 This can be selected by using the...

Page 83: ...of Cell Delineation Status in which frame is lost Detection If the OCD status lasts for T ms Termination If a non OCD status lasts for T ms T 4 ms or 0 ms This can be selected by using the LCDDT bit of the MDATMR register In the default mode T 4 ms When T 0 ms the detection termination condition is the same as that of OCD CD CD Pin State Change Indicates that the CD pin input goes low Detection If...

Page 84: ...d OCD LCD When LOS LOF Line AIS LOP or Path AIS is detected 2 Protection of the alarm detection When the µPD98413 detect the specific alarm the mPD98413 is protected the alarm detection and not detect corresponding alarm And if the corresponding alarm is in detecting condition that alarm is terminated automatically The protection and termination alarm is as follow Termination alarm Terminate condi...

Page 85: ...unter stop When the µPD98413 detect the specific alarm the corresponding alarm counter is stopped automatically The stop alarm counter is as follow Stop counter Counter stop condition B1 error counter When LOS or OOF is detected B2 error counter When LOS LOF or Line AIS is detected Line REI counter When LOS LOF Line AIS or Line RDI is detected B3 error counter When LOS LOF Line AIS LOP or Path AIS...

Page 86: ...PS signal is the same in three frames in a row the APS bit of the DSLER register is set to report the CPU The APS bit is not set as long as the same APS signals are received When the CPU detects that the APS bit has been set it reads the K12R register of the OH drop register to obtain the APS signal The K12R register is updated only if the same value has been received in three frames in succession...

Page 87: ...e same in band address to the IADR bit of working port and protection port of the PTADRT register 2 Transmit cell packet for port which is set by UADR bit the PTADRT register Note Take care of the transmit cell available signal When transmit cell packet to the port the uplink device must be conform the cell available signal of each port that is transmitted the same cell packet In the status pollin...

Page 88: ... FIFO of the protection port by the PnFCLS bit of the MDAPIR register And enable the protection port by setting the PnER bit of the PENB register 3 Disable the working Port by setting the PnER bit of the PENB register 4 After confirm that the working port FIFO is not busy by the PnBSY bit of the DGE and TGE register start the receive FIFO of the protection port by the PnFCLS bit of the MDAPIR regi...

Page 89: ...f the C2 byte is compared with 00h If the C2 byte is 00h the Path UNEQ is detected The detection and clearing conditions are as follows Detection If frames with the C2 byte being 00h are received n times continuously Clearing If frames with the C2 byte being the value other than 00h are received n times continuously n 3 or 5 This can be selected by using the PPLMM bit of the MDPOHR register In the...

Page 90: ... expect value 00h 00h Path UNEQ Path UNEQ 00h 01h None Matched Path PLM 00h XXh Path PLM Path PLM 01h 00h Path UNEQ Path PLM Path UNEQ Path PLM 01h 01h None Matched None Matched 01h XXh Path PLM Path PLM XXh 00h Path UNEQ Path PLM Path UNEQ Path PLM XXh 01h None Matched Path PLM XXh XXh None Matched None Matched XXh Yyh Path PLM Path PLM Note XXh anything except 00h or 01h YYh anything except 00h ...

Page 91: ... 8 BIP 8 operation is performed on all the bits in frames after frame descramble and the result of this operation is inserted in the B1 byte before frame scramble of the next frame then transmitted AU pointer AU pointer B1 After scramble Before scramble 1 frame 9 rows 1 frame 9 rows BIP operation range B1 BIP 8 operation result of preceding 1 080 bytes SOH SOH ii B2 byte Line BIP 96 BIP 96 operati...

Page 92: ...sult of preceding 1 044 bytes P O H Fixed stuff b Transmitting Line REI Line Remote Error Indication Whether Line BIP 96 error has occurred is reported to a unit in the upstream If a B2 error is detected in the receive frame the number of erroneous interleaved bit blocks is automatically stored to the M1 byte c Transmitting Path REI Path Remote Error Indication Whether Path BIP 8 error occurs is r...

Page 93: ...etection Path layer BIP 8 of the receive data is checked BIP 8 operation is performed on the STS 12c SPE area one frame before data after frame descramble and the result of the operation is verified against the value of the B3 byte of the current frame Line REI detection Line Remote Error Indication Line remote block error information Line REI is detected when a frame having the M1 byte set to the...

Page 94: ...r of cells modified due to the HEC verification Note Cell counters Receive FIFO full drop cell counter Number of dropped cells due to receive FIFO overflow Transmit valid packet counter Number of packets or bytes transmitted from the transmit FIFO to the line Transmit abort packet counter Number of abort packets transmitted from the transmit FIFO to the line Transmit FIFO underflow packet counter ...

Page 95: ...which the counter value is stored temporarily 1 The CPU sets the bits in the CSMPT and CSMPR register corresponding to the counter whose value is to be obtained to 1 2 The µPD98413 loads the count value at the time of the counter that has been set to 1 to the load register and clears the counter to 0 It also clears the bits of the CSMPT and CSMPR register to 0 3 The CPU reads the count value from ...

Page 96: ...NT frame one in which less than LT bit errors are detected is received MT consecutive times SD Signal Degrade Signal degrade alarm Detection A specific number of frames are defined as one frame to be monitored called the ND frame This alarm is detected when an ND frame one in which LD or more bit errors are detected is received MD consecutive times Termination A specific number of frames are defin...

Page 97: ...ietary 97 Example When MD 3 and MT 4 Ο Less than LD errors are detected in the ND frame LD or more errors are detected in the ND frame Less than LT errors are detected in the NT frame Ο N frame Three consecutive frames Four consecutive frames Degradation 1 indication 0 ...

Page 98: ...SDCCT 00 H SDCCR D2 SDCCT 00 H SDCCR SOH D3 SDCCT 00 H SDCCR K1 K12T 00 H K12R K2 K12T 00 H K12R D4 LDCCT1 00 H LDCCR1 D5 LDCCT1 00 H LDCCR1 D6 LDCCT1 00 H LDCCR1 D7 LDCCT2 00 H LDCCR2 D8 LDCCT2 00 H LDCCR2 D9 LDCCT2 00 H LDCCR2 D10 LDCCT3 00 H LDCCR3 D11 LDCCT3 00 H LDCCR3 D12 LDCCT3 00 H LDCCR3 S1 S1Z2E2T 00 H S1Z2E2R 1st Z2 S1Z2E2T 00 H S1Z2E2R E2 S1Z2E2T 00 H S1Z2E2R 1st Z2 bit6 7 Z2FDR LOH 1s...

Page 99: ...The contents of the drop registers except the K12R C2R Z2FDR and Z2FMR registers are updated each time a frame is received The K12R C2R Z2FDR and Z2FMR registers are updated in the following conditions K12R This register is updated if the values of the K1 and K2 are the same in three frames received continuously after the different value from that received previously is detected When this register...

Page 100: ...w message is set to Expected buffer a trace message is transmitted from buffer Table 3 19 Register and bits related trace message transmit Register and Bit of Section trace message Classificati on Section J0 Path J1 R W Outline Mode MDSOHT register J0SZ bit MDPOHT register J1SZ bit R W Selection of 16 or 64 byte length BSEL bit BSEL bit R W Selection of J0 buffer or J1 buffer Buffer select TMBT re...

Page 101: ... lower word 16 bit is not use See Figure 3 31 3 Upon the completion of writing to the highest address of the pointer incremented each time a write access occurs the pointer is automatically returned to 0 The highest address varies with the setting of the message length 4 The pointer register BADR bit of the TMBT register indicates the pointer value for the word to be written next By directly speci...

Page 102: ...s of TMBT register is setted to 00H 00H 00H 00H TMDT register reflect the DATA DATA DATA DATA for 00H to 03H of for 00H to 03H of for 00H to 03H of for 00H to 03H of J0 Expected Buffer J0 Expected Buffer J0 Expected Buffer J0 Expected Buffer 3EH 3FH b 16 bit access 16 bit access method is as follows Figure 3 31 The way to Access to transmit trace message buffer J0 Setting buffer J0 Setting buffer ...

Page 103: ...Register and bits related trace message receive Register and Bit of Section trace message Classificati on Section J0 Path J1 R W Outline MDSOHR register J0SZ bit MDPOHR register J1SZ bit R W Selection of 16 or 64 byte length Mode MDSOHR register J0SYNC bit MDPOHR register J1SYNC bit R W Specifies whether set synchronization pattern is at the beginning or end of message BSEL bit BSEL bit R W Select...

Page 104: ...ated When the data string stored in Captured buffer satisfies the three conditions listed below the data is stored in the Expected Buffer and the JLOCK bit of the CMTMR register is set to 0 and at the same time the J0M bit of the DPPER register is set to post notification of the arrival of a new message to the CPU The setting of the J0M bit can be used to trigger an interrupt If the J0LOCK bit of ...

Page 105: ...ins Note If TMDR register is accessed by 16 bit access the lower word 16 bit is not use See Figure 3 33 8 Each time the CPU has accessed the access register the µPD98413 automatically increments the pointer of the buffer Upon the completion of reading from the highest address of the pointer incremented each time a read is performed the pointer is automatically returned to 0 ...

Page 106: ...MDR register reflect the DATA DATA DATA DATA for 00H to 03H of for 00H to 03H of for 00H to 03H of for 00H to 03H of J0 Expected Buffer J0 Expected Buffer J0 Expected Buffer J0 Expected Buffer J0 Accepted buffer J0 Accepted buffer J0 Accepted buffer J0 Accepted buffer J1 Accepted buffer J1 Accepted buffer J1 Accepted buffer J1 Accepted buffer A 00H 01H 02H 03H 04H 05H B C D A B C D 00H 01H 02H 03H...

Page 107: ...or 00H to 01H of for 00H to 01H of for 00H to 01H of J0 Expected Buffer J0 Expected Buffer J0 Expected Buffer J0 Expected Buffer J0 Accepted buffer J1 Accepted buffer A 00H 01H 02H 03H 04H 05H B A B 00H 01H 02H 03H 04H 05H If the BADR bits of TMBR register is setted to 01H TMDR register refrect the DATA DATA DATA DATA for 01H to 02H of for 01H to 02H of for 01H to 02H of for 01H to 02H of J1 Expec...

Page 108: ... MDSOHR register continuously and that message equal to expected massage When the µPD98413 detects the Section TIM the status is indicated as the Section TIM in the DSLER register c Detecting J1 Path Trace Identifier Unstable Path TIU Whether the 16 or 64 byte section trace message stored in the J1 byte is received stably is checked If the message stored to the J1 message buffer differs from the p...

Page 109: ...re set in the PESOH register µPD98413 inverts the corresponding bits of B1 byte by the PB1 7 0 bits of the PESOH register If set to 01H in the PB1 7 0 field the LSB bit of the B1 byte is inverted B2 error PB2 frame PELOH register Inverts any bits of 12th B2 byte Inverted bits are set in the PELOH register µPD98413 inverts the corresponding bits of 1st B2 throw 12th B2 byte by the PB2 7 0 bits of t...

Page 110: ...e Instead a frame that is mapped Line AIS frame is transmitted If the ELPOM bit of the MDPGEN register is set the loop data can also be sent to the transmission line Figure 3 34 Equipment Loopback Tx FIFO Rx FIFO Tx ATM Processor Tx POS Processor Rx ATM Processor Rx POS Processor A T M P O S I n t e r f a c e Rx POH Processor Rx SOH Processor Tx POH Processor Tx SOH Processor 2 Line Loopback In th...

Page 111: ...e interface of the µPD98413 The transmit receive clock paths can be changed by setting pins and registers This block consists of parallel to serial MUX serial to parallel DEMUX TxPLL and clock and data recovery unit CDR Figure 4 1 Overview of µ µ µ µPD98413 line interface block TxPLL FRAMER0 TDOT0 TDOC0 RDIT0 RDIC0 RFCKTTL CDR DEMUX 0 1 8 MUX 0 8 1 CD0 CD CNT PORT 0 1 78MHz 78MHz RFCKPLT RFCKPLC 2...

Page 112: ...oth reference clock are internally ANDed to generate the reference for TxPLL and CDR If the LVTTL reference clock is used the positive side of the differential PECL RFCKPLT must be connected to a logic one and the negative side RFCKPLC to a logic zero If a differential PECL reference clock is used LVTTL reference clock input RFCKTTL must be tied high 3 Loop timing mode When the LPTIM bit of the MD...

Page 113: ...ion circuit judges that the CDR is in out of locked state OOL status This status is reflected on the bits of the status register and can be used as an interrupt cause If CDR enters the OOL status to prevent the receiver circuit from operating with an unstable clock the clock that provided to the receiver circuit after DEMUX be automatically changed to the TxPLL If the difference is within 500 ppm ...

Page 114: ...CHAPTER 4 INTERFACES PRELIMINARY NEC confidential and Proprietary 114 7 Connection example TBD ...

Page 115: ...cutes a parity check on transmit data generates and outputs a parity bit of receive data Detects transmit receive FIFO overflows Selectable FIFO threshold condition for TXCLAV signal indicating an available area of transmit FIFO for each port 1K bytes transmit and receive FIFOs for each port Supports an optional TAG field with transmit and receive cells 4 2 1 Signals An example of connecting the A...

Page 116: ...ive low signal and the assertion is coincident with the start of the cell transfer TXENB_B is used for address selection during the last clock cycle before it is asserted TXPRTY input Transmit data path parity TXPRTY is served as the odd or even parity over TXDATA 31 0 TXCLAV0 3 output Transmit cell buffer available TXCLAV is used to indicate that space for at least one cell is available in the µP...

Page 117: ...ble RXENB_B is an active low signal asserted by the ATM device to initiate a cell transfer RXENB_B is used for address selection during the last clock cycle before it is asserted RXPRTY output Receive data path parity RXPRTY serves as the odd or even parity over RXDATA RXCLAV0 3 input Receive cell available RXCLAV is used to indicate that at least one cell is available in the µPD98413 receive FIFO...

Page 118: ...H at the reception side It is internally dropped at the transmission side 1 UDF The µPD98413 supports a 52 byte cell format that does not include the H5 byte that is the HEC field of a cell overhead and a 56 byte format that includes If H5 is included dummy data UDF is also inserted In this manual the 56 byte cell format is referred to as mode with UDF and the 52 byte format as mode without UDF Th...

Page 119: ...status polling mode Multi PHY operation with 1 TXCLAV 1 Direct status indication The µPD98413 implements a dedicated TXCLAV signal for each of the ports TXCLAV0 corresponds to the port0 while TXCLAV3 corresponds to the port3 The ATM device can send a cell to the µPD98413 only when the port has indicated to the ATM device that it is ready to receive at least one complete cell The µPD98413 indicates...

Page 120: ...rt and this port indicates that it can receive the second cell In the case of back to back transfer the ATM device does not explicitly select the µPD98413 port and TXENB_B will not be deasserted The second cell is transferred immediately after the previous one and the TXSOC is asserted to indicate the start of cell This example is illustrated below Figure 4 6 Back to back Cell Transmission Direct ...

Page 121: ...high if the port can accept one or more complete ATM cells TXCLAV0 is driven low otherwise The TXCLAV0 is not applicable on the first cycle after TXSOC is asserted on this cycle the µPD98413 keeps the status before the transfer is started TXADDR 1 0 during the clock cycle before asserting the TXENB_B signal will select the port which will receive the next cell The µPD98413 will decode this signal ...

Page 122: ...ATM device can select a port for transfer of a cell when the port has indicated to the ATM device that it has at least one cell available The µPD98413 deasserts the RXCLAV0 3 coincident with RXSOC to indicate that the corresponding port of the µPD98413 has no subsequent cell available Once the RXCLAV0 3 has been asserted it will have to stay asserted until the RXSOC is asserted on that particular ...

Page 123: ...ACES PRELIMINARY NEC confidential and Proprietary 123 RXCLK RXENB_B RXSOC RXDATA 31 0 P12 X P11 H1 P8 P9 P10 X H1 X Invalid RXCLAV0 RXCLAV1 RXCLAV2 RXCLAV3 P10 P1 P2 P3 RXPRTY RXADDR 1 0 X PORT0 X P11 P12 X X PORT1 X X ...

Page 124: ...e µPD98413 on a per cell basis The ATM device can explicitly select the µPD98413 port for transfer of a cell only when the port has indicated to the ATM device that it has at least one cell available using the RXCLAV0 The ATM device polls by presenting the port address on RXADDR 1 0 The µPD98413 responds two clock cycles later by driving RXCLAV0 high if the port is ready to send one or more comple...

Page 125: ...he same port and the ATM device can receive the second cell In the case of back to back transfer the ATM device does not explicitly select the µPD98413 port as transfer to the same port is assumed The second cell is transferred immediately after the previous one and the RXSOC is asserted to indicate the start of cell This example is illustrated below Figure 4 12 Back to back Cell Reception Status ...

Page 126: ...M interface and indicates the error by the register 1 Transmit error At the transmit side of the ATM interface the µPD98413 detects the following errors and indicates the error by the APIET register Parity error UTOPIA Interface The µPD98413 checks a parity input by TXPRTY while TXENB_B is asserted If a parity error is detected the µPD98413 indicates the error by the APIET register Parity error Tr...

Page 127: ...tored in the receive FIFO and check the parity when receive cell is take out from the receive FIFO If a parity error is detected the µPD98413 indicate the error by the APIER register RXENB_B or RXSOC error If the µPD98413 is detect that RXENB_B is deasserted or RXSOC is asserted while a cell transfer the µPD98413 indicate the error by the APIER register Port select error If the µPD98413 select the...

Page 128: ...ecutes a parity check on transmit data generates and outputs a parity bit of receive data Selectable FIFO threshold condition for Transmit Packet Available TPA signal indicating an available area of transmit FIFO for each port 1K bytes transmit and receive FIFOs for each port 4 3 1 Signals An example of connecting the POS interface is shown below Figure 4 13 Example of Connecting the POS Interface...

Page 129: ... TSX is valid when TENB_B is high When TENB_B is low the TDAT TMOD TSOP TEOP and TERR signals are valid TSX is invalid when TENB_B is low TPRTY input Transmit bus parity TPRTY indicates the parity calculated over the TDAT bus TPRTY is considered valid only when TENB_B or TSX is asserted The µPD98413 supports the odd or even parity When the µPD98413 detects a parity error the µPD98413 indicates it ...

Page 130: ...dated on the rising edge of TFCLK STPA output Selected port transmit packet available STPA always provides status indication for the selected port The port which STPA reports is updated on the following rising edge of TFCLK after the µPD98413 samples the in band port address on TDAT STPA transitions high when a predefined minimum number of bytes is available in the transmit FIFO When STPA transiti...

Page 131: ... RERR RSX and RVAL signals are updated on the following rising edge of RFCLK When RENB_B is high the RDAT RPRTY RMOD RSOP REOP RERR RSX and RVAL signals will remain unchanged on the following rising edge of RFCLK RPRTY output Receive bus parity RPRTY indicates the parity calculated over the RDAT bus RPRTY is considered valid only when RVAL or RSX is asserted The µPD98413 supports the odd or even p...

Page 132: ...REOP and RERR signals are invalid RSX is valid when RVAL is low RSX output Receive start of transfer RSX indicates when the in band port address is presented on the RDAT bus When RSX is high and RVAL is low RDAT 7 0 is the in band port address selected port The in band port address specified the port can be set any value by the IADRR register By default the µPD98413 outputs the following addresses...

Page 133: ...lability information that indicated by DTPA and STPA is programmable by the FTHT1 and FTHT2 register If DTPA is asserted and the POS device is ready to transfer the transmit data it asserts TSX deasserts TENB_B and presents the port address on the TDAT bus Subsequent data transfers with TENB_B low are treated as packet data that is sent to the selected port At any time if the POS device does not h...

Page 134: ...transfer is same operation as the direct status indication mode Figure 4 16 Status Polling Timing TFCLK TADR 1 0 PORT0 PORT1 PORT2 PORT0 PORT1 PTPA PORT0 PORT3 PORT1 PORT2 PORT2 PORT0 PORT1 PORT2 PORT3 PORT3 PORT3 PORT0 PORT1 PORT2 PORT0 PORT1 PORT2 PORT3 DTPA0 DTPA1 DTPA2 DTPA3 4 3 4 Receive operation In the receive interface the µPD98413 selects the port by itself which there is a receive data i...

Page 135: ...CHAPTER 4 INTERFACES PRELIMINARY NEC confidential and Proprietary 135 ...

Page 136: ...RENB RSX RDAT 31 0 RPRTY RVAL A 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 A 2 D1 D2 Burst transfer size Idol Clock Idol Clock D3 3 In band address inserted receive operation This receive operation must be inserted the in band address after burst transfer disconnected and resume without the port change however the port is not changed This mode is enabled by the IADRM bit of the MDAPIR register Figure 4 19 I...

Page 137: ...gister 1 Transmit error At the transmit side of the POS interface the µPD98413 detects the following errors and indicates the error by the APIET register End Of Packet EOP error Wrong order for SOP and EOP The µPD98413 checks EOP Signal input by TEOP at end of every packet for each port If EOP is asserting before Start Of Packet SOP is asserted the µPD98413 is detect EOP error If EOP error is dete...

Page 138: ...tects the following errors and indicates the error by the APIER register Parity error Receive FIFO The µPD98413 is generate the parity when receive packet is stored in the receive FIFO and check the parity when receive packet is take out from the receive FIFO If a parity error is detected the µPD98413 indicate the error by the APIER register ...

Page 139: ...rface to use is selected by the MDPT register If both interfaces are enabled the overhead interface is take precedence Table 4 1 Correspondence table of multiplexed OH interface and DCC interface Pin Name OH Interface DCC Interface Pin Name OH Interface DCC Interface TOHCLK TOHCLK Not Use ROHCLK ROHCLK Not Use TTOHFP TTOHFP TSDCLK RTOHFP RTOHFP RSDCLK TPOHFP TPOHFP TLDCLK RPOHFP RPOHFP RLDCLK TOHA...

Page 140: ...rame Row1 2 Frame Row2 19 44MHz 1st A1 2nd A1 Z0 J1 B1 4 TOH 144 Clock 36 4 POH 4 Clock IDLE 122 Clock 270 Clock 4 4 4 TOHCK O TTOHFP O TPOHFP O TOHD 0 I TOHD 1 I TOHAV I Bit1 Bit3 Bit5 Bit7 Bit2 Bit4 Bit6 Bit8 Bit1 Bit3 Bit5 Bit7 Bit2 Bit4 Bit6 Bit8 Bit1 Bit3 Bit5 Bit7 Bit2 Bit4 Bit6 Bit8 Bit1 Bit3 Bit5 Bit7 Bit2 Bit4 Bit6 Bit8 Bit1 Bit3 Bit5 Bit7 Bit2 Bit4 Bit6 Bit8 Don t care peripheral device ...

Page 141: ...valid data to TOHD 1 0 The µPD98413 samples TOHAV at the clock edge of the first of the 4 cycles in which the one byte is input While TOHAV is high the bytes are input while it is low the bytes are ignored TOHAV is ignored at the edge of the next three cycles The insertion timing of the TOH information is allocated to all the TOH bytes of 36 bytes 9 rows However the TOH bytes shown in Table 4 5 ca...

Page 142: ...transmission takes precedence some bytes may be overwritten Table 4 6 OH Bytes That Cannot Be Changed When Alarm Is Transmitted K2 bits 6 8 The µPD98413 processing needed to transmit an alarm takes precedence and 110 is transmitted if the automatic return function of Line RDI is effected if the LRDI bit of the CMALM register is set or if 011 code is input to the TALMA C pins G1 bit 5 7 If the auto...

Page 143: ...sitive frequency justification POH doesn t sometimes exist Therefore in this case makes ROHAV low to show by the dotted line of figure 4 22 and doesn t output POH In case of negative frequency justification sometimes POH exists 2 bytes Therefore in this case ROHAV held high to show by the dotted line of figure 4 22 and output POH 2 bytes ROHAV is a signal by which the external OH controller is inf...

Page 144: ...b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b TLDCLK O 648KHz TLD I 3 TSDCLK 9 TLDCLK 4 4 4 Receive Section and Line DCC Extract Interface RSDCLK is a 216kHz RLDCLK is a 648kHz RSD is updated on the falling edge of RSDCLK RLD is updated on the falling edge of RLDCLK The D1 D3 and D4 D12 bytes shifted out of the µPD98413 in the frame shown are extracted...

Page 145: ...ort frame generated by the µPD98413 device to a system reference When detected the frame pulse input from external peripheral devices the µPD98413 starts transmit frame after fixed delay Therefore please avoid the usage every frame input TFPI is sampled on the own rising edge TFPI must be tied low if not use this pin TFPI is enabled by the setting of the TFPE bit of the MDPT register ...

Page 146: ... of the GPIN register of µPD98413 For each general purpose input port the GPIN register provides a pair of bits one representing the actual input level and the other indicating the reversed input level This pair of status bits and the mask setting of the GPIN_M register can be used to specify both negative transition from high to low and positive transition from low to high of the general purpose ...

Page 147: ...ne bit PRDI mode PRDI one bit PRDI G1 bit5 1 Enhanced PRDI mode PERDI Server defect G1 bit5 7 101 101 PERDI Connectivity defect G1 bit5 7 110 110 PERDI Payload defect G1 bit5 7 010 111 Reserved TALMx 0 corresponds to PORT0 while TALMx 3 corresponds to PORT3 Example TALMA 0 1 TALMB 0 0 TALMC 0 0 then the LAIS alarm is transmitted to port 0 4 7 2 Alarm Detection Pins Each port has 3 pins These pins ...

Page 148: ...ect signal UWE_B I Upper word enable signal R W_B I Read write select signal RDY_B O Ready signal INT_B O Interrupt Signal 4 8 1 Endian The microprocessor bus is set to little endian as the default condition after reset To connect a microprocessor with a big endian interface set the MIFM bit of the MDDGEN register to 1 The µPD98413 controls access by using AD1 address and UWE_B as follows To UWE_B...

Page 149: ...he next rising of MCLK When the µPD98413 negate RDY_B the microprocessor can deassert CS_B The microprocessor must deassert CS_B at least 1clock cycle Figure 4 25 Write Access Timing MCLK I AD 31 0 I O CS_B I RDY_B O R W_B I UWE_B I Address Data Address Read operation If R W_B is high a read operation is started When data output is ready the data is output to AD 31 0 in synchronization with the ri...

Page 150: ...CHAPTER 4 INTERFACES PRELIMINARY NEC confidential and Proprietary 150 MCLK I AD 31 0 I O CS_B I RDY_B O R W_B I UWE_B I Address Data Address ...

Page 151: ...sponding detailed cause register at the lower stage is set to 1 When the host detects that an interrupt signal has been asserted active it first reads the INT register second reads the GEV ICT and ICR registers and then reads the detailed cause register corresponding to the bit of the GEV ICT and ICR registers that has been set to identify the event that has occurred The bits of the GEV ICT and IC...

Page 152: ...ster INT MASK REGISTER GPIN MASK REGISTER APIER MASK REGISTER APIET MASK REGISTER ICR MASK REGISTER ICT MASK REGISTER Interrupt caused register TAPER REGISTER TSLER MASK REGISTER DPPER MASK REGISTER TPPER MASK REGISTER DAPER MASK REGISTER DSLER MASK REGISTER TAPER MASK REGISTER GPIN REGISTER GEV MASK REGISTER TGE REGISTER DGE REGISTER TGE MASK REGISTER DGE MASK REGISTER Table 4 7 Interrupt Port Re...

Page 153: ...register is set to 1 the DAPET bit in the ICT register is set Receive section and line layer event detection registers DSLER This register indicates that section and Line layer event has detected When at least one bit in the DSLER register is set to 1 the DSLER bit in the ICR register is set Receive section and line layer event termination registers TSLER This register indicates that section and L...

Page 154: ...nter overflow Reception of Line REI Detection of the Line REI counter overflow Reception of APS Automatic Protection Signal Storing J0 message has been completed DSLER TSLER CD pin input activation Detection and termination of high level of CD pin input DSLER TSLER Pointer and path layer defect and alarm detection and termination Detection and termination of Loss Of Pointer LOP Reception of Path A...

Page 155: ...on of the received short packet counter overflow DAPER TAPER Transmit ATM POS layer event detection and termination Detection of the transmit abort packet due to transmit FIFO underflow Detection of the transmitted valid cell packet counter overflow Detection of the transmitted abort packet counter overflow Detection of the transmit FIFO underflow packet counter overflow DAPET TAPET Receive ATM PO...

Page 156: ... of the detailed cause register is set or reset differs as shown below Table 4 11 Set and Reset Conditions of Detailed Cause Register and interrupt cause register Register Set Condition Reset Condition DGE DSLER register DPPER register DAPER register DAPET register Event detection Cleared by CPU TGE TSLER register TPPER register TAPER register Event termination Cleared by CPU ...

Page 157: ...cause When the CPU clears the LOS bit of the DSLER register the DSLER bit of the ICR register is also cleared to 0 and INT_B is deasserted inactive The LOS bit of the DSLER register remains set to 1 until it is cleared by the CPU If the LOS event ends the LOS bit of the TSLER register and TSLER bit of the ICR register are set and INT_B is asserted active again When the LOS bit of the TSLER registe...

Page 158: ...thod Register Read clear enable register Mask register Read clear address Read only Write clear address Detailed cause register Setting Clear Contents display Table 4 12 Functions of the Interrupt Cause Registers Access Destination Description Read clear address This address is used for reading the contents of the register and then for clearing the register Note that only those bits enabled in the...

Page 159: ...verhead byte in the SONET SDH frame in the order in which the bits are output from the line interface Description 2 D31 to D0 bits This description is mainly used to indicate the bits in an internal register of the µPD98413 The bits correspond to the AD31 to AD0 pins of the external CPU interface 1 Indicating bits in overhead byte Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 1 2 3 4 5 D31 D23 D...

Page 160: ...it POH mode R W 00000000 0050 0450 0850 0C50 MDATMT Transmit ATM mode R W 00000000 0054 0454 0854 0C54 MDPOST Transmit POS mode R W 00000000 0058 0458 0858 0C58 PACT Transmit POS Address and Control R W 000003FF 005C 045C 085C 0C5C HPTNT Transmit HALT pattern R W 00000000 0060 MDAPIT Transmit ATM POS interface mode R W 00000000 0064 0464 0864 0C64 FTHT1 ATM POS transmit FIFO threshold 1 R W 001000...

Page 161: ...100 00D4 04D4 08D4 0CD4 PEATM Transmit ATM pseudo error R W 00000000 00E0 04E0 08E0 0CE0 MDBER Bit error rate monitoring mode R W 00000202 00E4 04E4 08E4 0CE4 SFND SF detection N parameter R W 00000000 00E8 04E8 08E8 0CE8 SFLMD SF detection L and M parameter R W 00000000 00EC 04EC 08EC 0CEC SFNT SF termination N parameter R W 00000000 00F0 04F0 08F0 0CF0 SFLMT SF termination L and M parameter R W ...

Page 162: ...t port status mask R W 0000FFFF 01A0 GEV_RO General event read only R 00000000 01A4 GEV_M General event mask R W 00000003 01B0 05B0 09B0 0DB0 DAPET_RWC Transmit ATM POS layer event detection read only write clear R WC 00000000 01B4 05B4 09B4 0DB4 DAPET_RC Transmit ATM POS layer event detection read clear RC 00000000 01B8 05B8 09B8 0DB8 DAPET_RCE Transmit ATM POS layer event detection read clear en...

Page 163: ...lear R WC 00000003 0244 0644 0A44 0E44 DAPER_RC Receive ATM POS layer event detection read clear RC 00000003 0248 0648 0A48 0E48 DAPER_RCE Receive ATM POS layer event detection read clear enable R W 7FFF0003 024C 064C 0A4C 0E4C DAPER_M Receive ATM POS layer event detection mask R W 7FFF0003 0250 0650 0A50 0E50 TAPER_RWC Receive ATM POS layer event termination read only write clear R WC 00000000 02...

Page 164: ...4 B3ECR Receive B3 error counter load R 00000000 02E8 06E8 0AE8 0EE8 LREICR Receive Line REI counter load R 00000000 02EC 06EC 0AEC 0EEC PREICR Receive Path REI counter load R 00000000 02F0 06F0 0AF0 0EF0 PFJCR Receive Positive Frequency Justification counter load R 00000000 02F4 06F4 0AF4 0EF4 NFJCR Receive Negative Frequency Justification counter load R 00000000 02F8 06F8 0AF8 0EF8 VPCR Receive ...

Page 165: ...ansmit G1 F2 and H4 insert R W 00000000 0348 0748 0B48 0F48 Z345T Transmit Z3 Z4 and Z5 insert R W 00000000 0360 0760 0B60 0F60 J0R Receive J0 drop R 00000000 0364 0764 0B64 0F64 E1F1R Receive E1 and F1 drop R 00000000 0368 0768 0B68 0F68 SDCCR Receive Section DCC drop R 00000000 036C 076C 0B6C 0F6C K12R Receive K1 and K2 drop R 00000000 0370 0770 0B70 0F70 LDCCR1 Receive Line DCC drop 1 R 0000000...

Page 166: ...CHAPTER 5 REGISTERS PRELIMINARY NEC confidential and Proprietary 166 5 2 Register summary ...

Page 167: ...CHAPTER 5 REGISTERS PRELIMINARY NEC confidential and Proprietary 167 ...

Page 168: ...CHAPTER 5 REGISTERS PRELIMINARY NEC confidential and Proprietary 168 ...

Page 169: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved APIMM APIM MIFM Reserved Bit Field Function Default D31 D24 Reserved Set to 0 0 D23 D16 GPIOM 7 0 Selects the input or output of the general purpose I O pins 1 Output 0 Input 0 D15 D18 Reserved Set to 0 0 D8 APIMM Selects the multi PHY mode of ATM POS interface 1 Status polling 0 Direct status indication 0 D7 APIM Selects the function of ATM POS interfa...

Page 170: ...1 Enables the receive function of the port3 of the µPD98413 0 Disable 0 D6 P2ER 1 Enables the receive function of the port2 of the µPD98413 0 Disable 0 D5 P1ER 1 Enables the receive function of the port1 of the µPD98413 0 Disable 0 D4 P0ER 1 Enables the receive function of the port0 of the µPD98413 0 Disable 0 D3 P3ET 1 Enables the transmit function of the port3 of the µPD98413 0 Disable 0 D2 P2ET...

Page 171: ... set to 1 Set 0 to this bit to return the normal operation 0 Normal operation 0 D8 P3RSTR 1 Executes software reset of the receive function including DEMUX CDR block of the port3 This function is the reset condition while this bit is set to 1 Set 0 to this bit to return the normal operation 0 Normal operation 0 D7 P2RSTR 1 Executes software reset of the receive function including DEMUX CDR block o...

Page 172: ...n This function is the reset condition while this bit is set to 1 Set 0 to this bit to return the normal operation 0 Normal operation 0 D1 P1RSTT 1 Executes software reset of the transmit function of the port1 excepted TxPLL function This function is the reset condition while this bit is set to 1 Set 0 to this bit to return the normal operation 0 Normal operation 0 D0 P0RSTT 1 Executes software re...

Page 173: ... the VER register Register Name Address Access Default VER 000CH R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PRO MAJ MIN Bit Field Function Default D31 D12 Reserved 0 D11 D8 PRO Product version D7 D4 MAJ Major version D3 D0 MIN Minor version Note that contact NEC for the current version ...

Page 174: ...fault D31 D8 Reserved Set to 0 0 D7 POUT7 1 Outputs a high level from the PIO7 pin 0 Outputs a low level from the pin 0 D6 POUT6 1 Outputs a high level from the PIO6 pin 0 Outputs a low level from the pin 0 D5 POUT5 1 Outputs a high level from the PIO5 pin 0 Outputs a low level from the pin 0 D4 POUT4 1 Outputs a high level from the PIO4 pin 0 Outputs a low level from the pin 0 D3 POUT3 1 Outputs ...

Page 175: ...Bit Field Function Default D31 D17 Reserved Set to 0 0 D16 APM Selects the function of the ATM POS processor 1 ATM 0 POS 1 D15 D12 Reserved Set to 0 0 D11 ELPOM 1 Outputs loop data to the line in equipment loopback mode 0 Does not output loop data to the line in equipment loopback mode Line AIS frame is transmitted to the line 0 D10 Reserved Set to 0 0 D9 ELPM1 1 Sets Equipment loopback mode 0 Nor...

Page 176: ...9 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TFPE LDCCE SDCCE OHE Bit Field Function Default D31 D3 Reserved Set to 0 0 D3 TFPE Controls if the transmit SONET frame is aligned with TFPI signal when the active high transmit frame pulse is input 1 Enable 0 Disable 0 D2 LDCCE Controls the function of the Line DCC insert interface 1 Enable 0 Disable 0 D1 SDCCE Controls the functi...

Page 177: ...H 0428H 0828H 0C28H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LDCCE SDCCE OHE Bit Field Function Default D31 D3 Reserved Set to 0 0 D2 LDCCE Controls the function of the Line DCC extract interface 1 Enable 0 Disable 0 D1 SDCCE Controls the function of the Section DCC extract interface 1 Enable 0 Disable 0 D0 OHE Controls ...

Page 178: ...ot indicated 0 D19 OCD 1 OCD event is indicated 0 OCD event is not indicated 0 D18 PTIU 1 Path TIU event is indicated 0 Path TIU event is not indicated 0 D17 PTIM 1 Path TIM event is indicated 0 Path TIM event is not indicated 0 D16 PPLU 1 Path PLU event is indicated 0 Path PLU event is not indicated 0 D15 PUNEQ 1 Path UNEQ event is indicated 0 Path UNEQ event is not indicated 0 D14 PPLM 1 Path PL...

Page 179: ... STIU 1 Section TIU event is indicated 0 Section TIU event is not indicated 0 D3 STIM 1 Section TIM event is indicated 0 Section TIM event is not indicated 0 D2 LOF 1 LOF event is indicated 0 LOF event is not indicated 0 D1 OOF 1 OOF event is indicated 0 OOF event is not indicated 0 D0 LOS 1 LOS event is indicated 0 LOS event is not indicated 0 ...

Page 180: ...s Z0M Bit Field Function Default D31 D6 Reserved Set to 0 0 D5 FSCM Controls scramble of a frame 1 Not scramble 0 Scramble 0 D4 J0SZ Selects the size of the transmit J0 section trace message 1 16 bytes 0 64 bytes 0 D3 B1M Selects even or odd parity for BIP 8 B1 parity operation of transmit section 1 Odd parity 0 Even parity 0 D2 UUBM Selects a value to be inserted in the unused byte area of the se...

Page 181: ...24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ALRDIM B2M UUBM Bit Field Function Default D31 D3 Reserved Set to 0 0 D2 ALRDIM Controls the automatic loopback transmission function of Line RDI 1 Not automatic loopback 0 Automatic loopback 0 D1 B2M Selects even or odd parity for BIP 96 B2 parity operation of transmit line 1 Odd parity 0 Even parity 0 D0 UUBM Sele...

Page 182: ...it pointer operation Address Register Name Port0 Port1 Port2 Port3 Access Default MDPTRT 0048H 0448H 0848H 0C48H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SS 1 0 Bit Field Function Default D31 D2 Reserved Set to 0 0 D1 D0 SS 1 0 Sets the contents of the SS bits of the transmit pointer 0 ...

Page 183: ... of Enhanced Path RDI connectivity 1 Includes Path TIU 0 Does not include Path TIU 0 D5 PTIMO Specifies whether Path TIM detection is included in the condition of automatic loopback transmission of Enhanced Path RDI connectivity 1 Includes Path TIM 0 Does not include Path TIM 0 D4 LCDO Specifies whether LCD detection is included in the condition of automatic loopback transmission of Path RDI 1 Inc...

Page 184: ...50H 0450H 0850H 0C50H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HECO CSCM IVCM Bit Field Function Default D31 D3 Reserved Set to 0 0 D2 HECO Controls the HEC insertion to a transmit cell 1 Disabled 0 Enabled 0 D1 CSCM Controls scramble of a cell 1 Not scramble 0 Scramble 0 D0 IVCM Selects the format of an invalid cell to ...

Page 185: ...5 HALTM Sets the HALT mode 1 HALT mode 0 Normal operation 0 D4 PSCM Controls scramble of a packet 1 Not scramble 0 Scramble 0 D3 FCSLM Selects the FCS calculation order whether it is calculated from the LSB or MSB of the transmit packet 1 MSB first 0 LSB first 0 D2 FCSSZ Selects the transmit FCS length 1 16 bits 0 32 bits 0 D1 FCSM Controls the insertion of FCS field in the transmit packet 1 Disab...

Page 186: ...efault PACT 0058H 0458H 0858H 0C58H R W 000003FF H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTLIN 7 0 ADRIN 7 0 Bit Field Function Default D31 D16 Reserved Set to 0 0 D15 D8 CTLIN 7 0 Sets the Control value inserted into the transmit packet 03H D7 D0 ADRIN 7 0 Sets the Address value inserted into the transmit packet FFH ...

Page 187: ...Port2 Port3 Access Default HPTNT 005CH 045CH 085CH 0C5CH R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SPTN 7 0 Bit Field Function Default D31 D8 Reserved Set to 0 0 D7 D0 SPTN 7 0 Sets the suspended pattern during the packet transmission Set the value except 5D 5E 7D 0H ...

Page 188: ... of port3 to port 0 1 Stop 0 Normal operation 0 D10 P2FSTP Stops the data output from the transmit FIFO of port3 to port 0 1 Stop 0 Normal operation 0 D9 P1FSTP Stops the data output from the transmit FIFO of port3 to port 0 1 Stop 0 Normal operation 0 D8 P0FSTP Stops the data output from the transmit FIFO of port3 to port 0 1 Stop 0 Normal operation 0 D7 D3 Reserved Set to 0 0 D2 TAGM Selects whe...

Page 189: ...7 0 Bit Field Function Default D31 D24 Reserved Set to 0 0 D23 D16 PLOW 7 0 Sets the low threshold which the TPA signal is asserted when the number of words 32 bit width for the transmit FIFO space is higher than this field 10 H D15 D8 Reserved Set to 0 0 D7 D0 APHIGH 7 0 ATM mode Sets the high threshold which the TCLAV signal is deasserted when the number of words 32 bit width for the transmit FI...

Page 190: ...C68 H R W 00000010 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PINI 7 0 Bit Field Function Default D31 D9 Reserved Set to 0 0 D8 D0 PINI 7 0 Sets the initial number of bytes when uPD98413 start to transmit the POS packet The uPD98413 start to transmit the data when either the number of words 32 bit width stored in the transmit FIFO exce...

Page 191: ... W 00000000 H 00010001 H 00020002 H 00030003 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UADR 1 0 IADR 7 0 Bit Field Function Default D31 D10 Reserved Set to 0 0 D9 D8 UADR 1 0 UTOPIA mode Sets the transmit port address for UTOPIA POS PHY mode Sets the polling address for POS PHY Port0 0 Port1 1 Port2 2 Port3 3 D7 D0 IADR 7 0 Sets the t...

Page 192: ...tus lasts for 3 ms LOF status is terminated if the µPD98413 is not in the OOF status for 3ms 0 LOF status is detected at the same time as OOF detection LOF status is terminated at the same time as OOF termination 1 D9 D8 OOFT 1 0 Changes the number of backward protection stages δ for OOF detection The OOF status is cleared if the frame synchronization pattern has been detected in the receive cell ...

Page 193: ...3 D2 LOST Selects LOS termination condition 1 Bellcore mode 0 ANSI mode 0 D1 Reserved Set to 0 0 D0 CDO Includes low level of the CD pin input in the LOS detection condition 1 LOS status if the CD pin input goes low 0 Not LOS status even if the CD pin input goes low 0 ...

Page 194: ...H 0874 H 0C74 H R W 0D0A0000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 J0PTN 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 J0M 15 0 Bit Field Function Default D31 D16 J0PTN 15 0 Sets the synchronous pattern of J0 trace message 0D0A H D15 D0 J0M 15 0 Sets the mask value of the synchronous pattern When the bits of this field is set to 1 the corresponding bits of synchronous pattern are masked 0...

Page 195: ...it Field Function Default D31 D4 Reserved Set to 0 0 D3 LRDIDT Changes n of the Line RDI detection condition Line RDI is detected when a frame with K2 byte bits 6 to 8 being 110 has been received n times 1 n 5 0 n 3 1 D2 LAISDT Changes n of the Line AIS detection condition Line AIS is detected when a frame with the K2 byte bits 6 to 8 set to 111 has been received n times 1 n 5 0 n 3 1 D1 B2M Selec...

Page 196: ... 1 Corresponding Conc STS is 3 x conc_ind or 1st STS is NDF_enable and all Conc STS is conc_ind 0 Corresponding Conc STS is 3 x conc_ind 0 D15 AIST2 Selects the AIS termination condition by NDF_enable whether include conc_ind of all H1 2 and H2 2 to H1 12 and H2 12 Concatenation Interpretation 1 Not include 0 Include 0 D14 AIST1 Selects the AIS termination condition by 3 x norm_point whether Inclu...

Page 197: ...ages n for LOP detection in status transition of pointer processing 11 Reserved 10 n 10 01 n 9 00 n 8 00 D6 Reserved Set to 0 0 D5 D4 SS 1 0 Sets the expected value of the SS bits to be verified if the SS bits are checked when the receive pointer action is identified when SSM 1 10 D3 SSM Selects whether the SS bits are checked when the receive pointer action is identified 1 Checked 0 Don t care 0 ...

Page 198: ... the Path RDI function 1 Enhanced Path RDI 0 One bit Path RDI 0 D10 J1MSG Changes n of the received trace message drop condition 1 n 5 0 n 3 1 D9 PTIUT Changes n of the Path TIU termination condition 1 n 5 0 n 3 1 D8 PTIUD Changes n of the Path TIU detection condition 1 n 8 0 n 5 1 D7 PTIMDT Changes n of the Path TIM detection termination condition 1 n 5 0 n 3 1 D6 PPLUT Changes n of the Path PLU ...

Page 199: ... NEC confidential and Proprietary 199 D1 J1SZ Selects the size of the receive J1 path trace message 1 16 bytes 0 64 bytes 0 D0 B3M Selects even or odd parity for BIP 8 B3 parity operation of receive line 1 Odd parity 0 Even parity 0 ...

Page 200: ... H 0884 H 0C84 H R W 0D0A0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 J1PTN 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 J1M 15 0 Bit Field Function Default D31 D16 J1PTN 15 0 Sets the synchronous pattern of J1 trace message 0D0AH D15 D0 J1M 15 0 Sets the mask value of the synchronous pattern When the bits of this field is set to 1 the corresponding bits of synchronous pattern are masked 00...

Page 201: ...CD status is terminated if cell synchronization status lasts for 4ms 0 LCD status is detected at the same time as OCD detection LCD status is terminated at the same time as OCD termination 1 D6 D5 OCDT 1 0 Changes the number of backward protection stages δ for OCD detection The OCD status is cleared if the correct HEC has been detected in the receive cell stream δ 1 times in a row 11 8 10 7 01 6 0...

Page 202: ... 2 0 CLPM Bit Field Function Default D31 D16 Reserved Set to 0 0 D15 D12 GFC 3 0 0000 D11 D9 PTI 2 0 000 D8 CLP A receive cell with VPI VCI being all 0 is verified with the pattern that is the cell header area other than the VPI VCI area set in this area The cell that coincides with the pattern in this area is not stored to the receive FIFO but dropped However the bit that is masked by the low ord...

Page 203: ...f the receive FCS is passed through the POS interface or stripped 1 FCS is passed 0 FCS is stripped 0 D4 FCSLM Selects the FCS calculation order whether it is calculated from the LSB or MSB of the receive packet 1 MSB first 0 LSB first 0 D3 FCSSZ Selects the receive FCS length 1 16 bits 0 32 bits 0 D2 FCSM Controls the check function of FCS field in the receive packet 1 Disabled FCS field are not ...

Page 204: ...efault D31 D16 Reserved Set to 0 0 D15 D8 CTLEX 7 0 Sets the expected value of the receive Control byte 03H D7 D0 ADREX 7 0 Sets the expected value of the receive Address byte FFH 32 Receive HALT pattern register HPTNR Address Register Name Port0 Port1 Port2 Port3 Access Default HPTNR 0098 H 0498 H 0898 H 0C98 H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11...

Page 205: ...than this length are indicated with short packet error This length is defined as the number of payload bytes received POS packet 0H 34 Receive packet length register 2 PLENR2 The PLENR2 register sets the receive packet length Address Register Name Port0 Port1 Port2 Port3 Access Default PLENR2 00A0 H 04A0 H 08A0 H 0CA0 H R W 000005FC H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved LLEN 2...

Page 206: ... data input into the receive FIFO of port0 1 Stop 0 Normal operation 0 D7 D5 Reserved Set to 0 0 D4 IADRM Sets the insertion of the receive in band address even if the receive burst transfer is disconnected and resume without the port change 1 In band address is inserted every receive transfer 0 In band address is not inserted when no port change 0 D3 IDLM Sets the idle clocks RFCLK inserted after...

Page 207: ...8 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PINI 7 0 Bit Field Function Default D31 D8 Reserved Set to 0 0 D7 D0 PINI 7 0 Sets the initial number of words 32 bit width when uPD98413 start to send the received POS packet to the POS device via receive POS interface The uPD98413 start to send the data when either the number of words 32 bit width store...

Page 208: ...t3 0CAC H R W 00000000 H 00000101 H 00000202 H 00000303 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UADR 1 0 IADR 7 0 Bit Field Function Default D31 D10 Reserved Set to 0 0 D9 D8 UADR 1 0 Sets the receive port address for UTOPIA Port0 0 H Port1 1 H Port2 2 H Port3 3 H D7 D0 IADR 7 0 UTOPIA mode Sets the value of TAG field added to the r...

Page 209: ...r 100 Transmission of ERDI P Server defect frame G1 bit5 7 101 ERDI P Server defect frames are successively transmitted while this field are set to 100 101 Transmission of ERDI P Connectivity defect frame G1 bit5 7 110 ERDI P Connectivity defect frames are successively transmitted while this field are set to 101 110 Transmission of ERDI P Payload defect frame G1 bit5 7 010 ERDI P Payload defect fr...

Page 210: ...ction Default D31 D16 Reserved Set to 0 0 D15 D8 PB1 7 0 Sets pseudo B1 error frame Pseudo B1 error frames are inverted the corresponding bits of B1 byte set to 1 in this field 1 H D7 D3 Reserved Set to 0 0 D2 PB1E 1 Transmits pseudo frame for B1 error generation Pseudo frames are successively transmitted while this bit is 1 Pseudo error frames are set in the PB1 field 0 Normal operation 0 D1 POOF...

Page 211: ...24 Reserved Set to 0 0 D23 D16 PM1 7 0 Sets pseudo Line REI error frame M1 byte is set to any value in this field as Pseudo Line REI error frames 01 H D15 D8 PB2 7 0 Sets pseudo B2 error frame Pseudo B2 error frames are inverted the corresponding bits of 12th B2 byte set to 1 in this field 01 H D7 D2 Reserved Set to 0 0 D1 PLREI 1 Transmits pseudo frame for Line REI generation Pseudo frames are su...

Page 212: ...function Address Register Name Port0 Port1 Port2 Port3 Access Default PEPTR 00CC H 04CC H 08CC H 0CCC H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PLOP Bit Field Function Default D31 D1 Reserved Set to 0 0 D0 PLOP 1 Transmits pseudo frame for LOP generation Pseudo frames are successively transmitted while this bit is 1 0 N...

Page 213: ...Reserved Set to 0 0 D19 D16 PG1 3 0 Sets pseudo Path REI error frame Bit 1 to 4 of G1 byte is set to any value in this field as Pseudo Path REI error frames 1H D15 D8 PB3 7 0 Sets pseudo B3 error frame Pseudo B3 error frames are inverted the corresponding bits of B3 byte set to 1 in this field 1H D7 D2 Reserved Set to 0 0 D1 PPREI 1 Transmits pseudo frame for Path REI generation Pseudo frames are ...

Page 214: ...on Address Register Name Port0 Port1 Port2 Port3 Access Default PEATM 00D4 H 04D4 H 08D4 H 0CD4 H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved POCD Bit Field Function Default D31 D1 Reserved Set to 0 0 D0 POCD 1 Transmits pseudo frame for OCD LCD generation Pseudo frames are successively transmitted while this bit is 1 0 Nor...

Page 215: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SDM 1 0 Reserved SFM 1 0 Bit Field Function Default D31 D10 Reserved Set to 0 0 D9 D8 SDM 1 0 Selects the source and enable which SD condition of the bit error rate monitoring is detected 11 B3 errors 10 B2 errors 01 B1 errors 00 Disable 10 D7 D2 Reserved Set to 0 0 D1 D0 SFM 1 0 Selects the source and...

Page 216: ...n 0 46 SF detection L and M parameters register SFLMD This register sets the parameters of SF detection Address Register Name Port0 Port1 Port2 Port3 Access Default SFLMD 00E8 H 04E8 H 08E8 H 0CE8 H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved LD 11 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LD 7 0 MD 7 0 Bit Field Function Default D31 D20 Reserved Set to 0 0 D19 D8 LD 11 0...

Page 217: ... 48 SF termination L and M parameters register SFLMT This register sets the parameters of SF termination Address Register Name Port0 Port1 Port2 Port3 Access Default SFLMT 00F0 H 04F0 H 08F0 H 0CF0 H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved LT 11 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LT 7 0 MT 7 0 Bit Field Function Default D31 D20 Reserved Set to 0 0 D19 D8 LT 11 ...

Page 218: ...n 0 50 SD detection L and M parameters register SDLMD This register sets the parameters of SD detection Address Register Name Port0 Port1 Port2 Port3 Access Default SDLMD 00F8 H 04F8 H 08F8 H 0CF8 H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved LD 11 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LD 7 0 MD 7 0 Bit Field Function Default D31 D20 Reserved Set to 0 0 D19 D8 LD 11 0...

Page 219: ... 52 SD termination L and M parameters register SDLMT This register sets the parameters of SD termination Address Register Name Port0 Port1 Port2 Port3 Access Default SDLMT 0100 H 0500 H 0900 H 0D00 H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved LT 11 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LT 7 0 MT 7 0 Bit Field Function Default D31 D20 Reserved Set to 0 0 D19 D8 LT 11 ...

Page 220: ...s Default TMBT 0110 H 0510 H 0910 H 0D10 H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved LT 11 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BSEL Reserved BADR 5 0 Bit Field Function Default D31 D9 Reserved Set to 0 0 D8 BSEL Selects the section or path trace message buffer 1 J1 buffer 0 J0 buffer 0 D7 D6 Reserved Set to 0 0 D5 D0 BADR 5 0 Sets the offset address of th...

Page 221: ...cess Default TMDT 0114 H 0514 H 0914 H 0D14 H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDAT 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BDAT 15 0 Bit Field Function Default D31 D0 BDAT 31 0 32 bit data of the trace message buffer When read access the data will be read from the trace message buffer set by TMBT register When write access the data will be written into the trace ...

Page 222: ...2 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved J1E J0E J1STAT J0STAT Bit Field Function Default D31 D4 Reserved Set to 0 0 D3 J1E Enables to transmit the path trace message 1 Enable 0 Disable 0 D2 J0E Enables to transmit the section trace message 1 Enable 0 Disable 0 D1 J1STAT Starts to transmit new path trace message 1 Transmits new message 0 Does not change message 0...

Page 223: ... H 0D1C H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BSEL Res BTYP BADR 5 0 Bit Field Function Default D31 D9 Reserved Set to 0 0 D8 BSEL Selects the section or path trace message buffer 1 J1 buffer 0 J0 buffer 0 D7 Reserved Set to 0 0 D6 BTYP Selects the message buffer 1 Accepted buffer 0 Expected buffer 0 D5 D0 BADR 5 0 ...

Page 224: ... from the trace message buffer set by TMBR register When write access the data will be written into the trace message buffer set by TMBR register 0H 58 Receive trace message command register CMTMR This register controls the receive trace message Address Register Name Port0 Port1 Port2 Port3 Access Default CMTMR 0124 H 0524 H 0924 H 0D24 H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 225: ...1 Indicates that the receive interrupt occurs in Port3 0 Corresponding ICR register is all 0 0 D7 P2ICR 1 Indicates that the receive interrupt occurs in Port2 0 Corresponding ICR register is all 0 0 D6 P1ICR 1 Indicates that the receive interrupt occurs in Port1 0 Corresponding ICR register is all 0 0 D5 P0ICR 1 Indicates that the receive interrupt occurs in Port0 0 Corresponding ICR register is a...

Page 226: ...16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved GEV GPIN APIER P3ICR P2ICR P1ICR P0ICR APIET P3ICT P2ICT P1ICT P0ICT Bit Field Function Default D31 D12 Reserved Set to 0 All 0 D11 GEV 1 Mask 0 Unmask 1 D10 GPIN 1 Mask 0 Unmask 1 D9 APIER 1 Mask 0 Unmask 1 D8 P3ICR 1 Mask 0 Unmask 1 D7 P2ICR 1 Mask 0 Unmask 1 D6 P1ICR 1 Mask 0 Unmask 1 D5 P0ICR 1 Mask 0 Unmask 1 D4 APIET 1 Mask 0 Unmask ...

Page 227: ...DAPET Bit Field Function Default D31 D1 Reserved Reserved All 0 D0 DAPET 1 Indicates that the bits of the DAPET register are set 0 DAPET register is all 0 0 62 Transmit interrupt cause Mask register ICT_M The ICT_M register is mask register of the ICT register Address Register Name Port0 Port1 Port2 Port3 Access Default Function ICT_M 0154 H 0554 H 0954 H 0D54 H R W 00000001 H Mask register 31 30 ...

Page 228: ...cause TXCLAV or TPA is ignored and transmit FIFO overflow occurs for port 3 0 Does not detect 0 D18 P2DDE 1 Detects a cell or packet discard because TXCLAV or TPA is ignored and transmit FIFO overflow occurs for port 2 0 Does not detect 0 D17 P1DDE 1 Detects a cell or packet discard because TXCLAV or TPA is ignored and transmit FIFO overflow occurs for port 1 0 Does not detect 0 D16 P0DDE 1 Detect...

Page 229: ...acket on POS PHY mode APIM 0 in MDDGEN and APM 0 in MDPGEN This field is no function and always 0 uPD98413 does not indicate this error 0 D10 P2CE UTOPIA mode APIM 1 in MDDGEN 1 Detects that TXENB_B is deasserted or TXSOC is asserted while a cell transfer of port 2 0 Does not detect Cell on POS PHY mode APIM 0 in MDDGEN and APM 1 in MDPGEN 1 Detects that the data size is not 53 bytes from TSOP to ...

Page 230: ...etects a parity error in the transmit FIFO RAM B of port 3 0 Does not detect 0 D6 P3PEA 1 Detects a parity error in the transmit FIFO RAM A of port 3 0 Does not detect 0 D5 P2PEB 1 Detects a parity error in the transmit FIFO RAM B of port 2 0 Does not detect 0 D4 P2PEA 1 Detects a parity error in the transmit FIFO RAM A of port 2 0 Does not detect 0 D3 P1PEB 1 Detects a parity error in the transmi...

Page 231: ...A P1PEB P1PEA P0PEB P0PEA Bit Field Function Default D31 D21 Reserved Reserved All 0 D20 PARE 1 Enable 0 Disable 1 D19 P3DDE 1 Enable 0 Disable 1 D18 P2DDE 1 Enable 0 Disable 1 D17 P1DDE 1 Enable 0 Disable 1 D16 P0DDE 1 Enable 0 Disable 1 D15 P3SEPE 1 Enable 0 Disable 1 D14 P2SEPE 1 Enable 0 Disable 1 D13 P1SEPE 1 Enable 0 Disable 1 D12 P0SEPE 1 Enable 0 Disable 1 D11 P3CE 1 Enable 0 Disable 1 D10...

Page 232: ...A P2PEB P2PEA P1PEB P1PEA P0PEB P0PEA Bit Field Function Default D31 D21 Reserved Set to 0 All 0 D20 PARE 1 Mask 0 Unmask 1 D19 P3DDE 1 Mask 0 Unmask 1 D18 P2DDE 1 Mask 0 Unmask 1 D17 P1DDE 1 Mask 0 Unmask 1 D16 P0DDE 1 Mask 0 Unmask 1 D15 P3SEPE 1 Mask 0 Unmask 1 D14 P2SEPE 1 Mask 0 Unmask 1 D13 P1SEPE 1 Mask 0 Unmask 1 D12 P0SEPE 1 Mask 0 Unmask 1 D11 P3CE 1 Mask 0 Unmask 1 D10 P2CE 1 Mask 0 Unm...

Page 233: ...TAPER 1 Indicates that the bits of the TAPER register are set 0 TAPER register is all 0 0 D6 DAPER 1 Indicates that the bits of the DAPER register are set 0 DAPER register is all 0 0 D5 Reserved Reserved All 0 D4 TPPER 1 Indicates that the bits of the TPPER register are set 0 TPPER register is all 0 0 D3 DPPER 1 Indicates that the bits of the DPPER register are set 0 DPPER register is all 0 0 D2 R...

Page 234: ...D74 H R W 000001FF H Mask register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Res TAPER DAPER Res TPPER DPPER Res TSLER DSLER Bit Field Function Default D31 D9 Reserved Set to 0 0 D8 Reserved Set to 1 1 D7 TAPER 1 Mask 0 Unmask 1 D6 DAPER 1 Mask 0 Unmask 1 D5 Reserved Set to 1 1 D4 TPPER 1 Mask 0 Unmask 1 D3 DPPER 1 Mask 0 Unmask 1 D2 Re...

Page 235: ...CLAV is low not active 0 Does not detect POS PHY mode APIM 0 in MDDGEN This field is no function and always 0 uPD98413 does not indicate this error 0 D14 P2PSE UTOPIA mode APIM 1 in MDDGEN 1 Detects that port2 is selected although the corresponding RXCLAV is low not active 0 Does not detect POS PHY mode APIM 0 in MDDGEN This field is no function and always 0 uPD98413 does not indicate this error 0...

Page 236: ...s error 0 D8 P0CE UTOPIA mode APIM 1 in MDDGEN 1 Detects that RXENB_B is deasserted while a cell transfer of port 0 0 Does not detect POS PHY mode APIM 0 in MDDGEN This field is no function and always 0 uPD98413 does not indicate this error 0 D7 P3PEB 1 Detects a parity error in the receive FIFO RAM B of port 3 0 Does not detect 0 D6 P3PEA 1 Detects a parity error in the receive FIFO RAM A of port...

Page 237: ...P2PSE P1PSE P0PSE P3CE P2CE P1CE P0CE P3PEB P3PEA P2PEB P2PEA P1PEB P1PEA P0PEB P0PEA Bit Field Function Default D31 D16 Reserved Reserved All 0 D15 P3PSE 1 Enable 0 disable 1 D14 P2PSE 1 Enable 0 disable 1 D13 P1PSE 1 Enable 0 disable 1 D12 P0PSE 1 Enable 0 disable 1 D11 P3CE 1 Enable 0 disable 1 D10 P2CE 1 Enable 0 disable 1 D9 P1CE 1 Enable 0 disable 1 D8 P0CE 1 Enable 0 disable 1 D7 P3PEB 1 En...

Page 238: ...3PSE P2PSE P1PSE P0PSE P3CE P2CE P1CE P0CE P3PEB P3PEA P2PEB P2PEA P1PEB P1PEA P0PEB P0PEA Bit Field Function Default D31 D16 Reserved Reserved All 0 D15 P3PSE 1 mask 0 unmask 1 D14 P2PSE 1 mask 0 unmask 1 D13 P1PSE 1 mask 0 unmask 1 D12 P0PSE 1 mask 0 unmask 1 D11 P3CE 1 mask 0 unmask 1 D10 P2CE 1 mask 0 unmask 1 D9 P1CE 1 mask 0 unmask 1 D8 P0CE 1 mask 0 unmask 1 D7 P3PEB 1 mask 0 unmask 1 D6 P3...

Page 239: ...he PIO5 pin 1 Low 0 High D12 PIN4L Inverts and indicates the input level of the PIO4 pin 1 Low 0 High D11 PIN3L Inverts and indicates the input level of the PIO3 pin 1 Low 0 High D10 PIN2L Inverts and indicates the input level of the PIO2 pin 1 Low 0 High D9 PIN1L Inverts and indicates the input level of the PIO1 pin 1 Low 0 High D8 PIN0L Inverts and indicates the input level of the PIO0 pin 1 Low...

Page 240: ...7L PIN6L PIN5L PIN4L PIN3L PIN2L PIN1L PIN0L PIN7H PIN6H PIN5H PIN4H PIN3H PIN2H PIN1H PIN0H Bit Field Function Default D31 D16 Reserved Reserved 0 D15 PIN7L 1 mask 0 unmask 1 D14 PIN6L 1 mask 0 unmask 1 D13 PIN5L 1 mask 0 unmask 1 D12 PIN4L 1 mask 0 unmask 1 D11 PIN3L 1 mask 0 unmask 1 D10 PIN2L 1 mask 0 unmask 1 D9 PIN1L 1 mask 0 unmask 1 D8 PIN0L 1 mask 0 unmask 1 D7 PIN7H 1 mask 0 unmask 1 D6 ...

Page 241: ... Reserved Reserved 0 D1 TGE 1 Indicates that the bits of the TGE register are set 0 TGE register is all 0 0 D0 DGE 1 Indicates that the bits of the DGE register are set 0 DGE register is all 0 0 74 General event Mask register GEV_M Common register The GEV_M register is mask register of GEV register Register Name Address Access Default Function GEV_M 01A4 H R W 00000003 H Mask register 31 30 29 28 ...

Page 242: ...ead clear 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FUPCT APCT VPCT ABOE Bit Field Function Default D31 D4 Reserved Reserved All 0 D3 FUPCT 1 Detects occurrence of an overflow in transmit FIFO underflow packet counter 0 Does not detect 0 D2 APCT 1 Detects occurrence of an overflow in transmit abort packet counter 0 Does not detect 0 D1 ...

Page 243: ...egister Name Port0 Port1 Port2 Port3 Access Default Function DAPET_RCE 01B8 H 05B8 H 09B8 H 0DB8 H R W 0000007F H Read clear enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FUPCT APCT VPCT ABOE Bit Field Function Default D31 D4 Reserved Set to 0 All 0 D3 FUPCT 1 enable 0 disable 1 D2 APCT 1 enable 0 disable 1 D1 VPCT 1 enable 0 disable...

Page 244: ...er Name Port0 Port1 Port2 Port3 Access Default Function DAPET_M 01BC H 05BC H 09BC H 0DBC H R W 0000007F h Mask register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FUPCT APCT VPCT ABOE Bit Field Function Default D31 D7 Reserved Set to 0 All 0 D3 FUPCT 1 mask 0 unmask 1 D2 APCT 1 mask 0 unmask 1 D1 VPCT 1 mask 0 unmask 1 D0 ABOE 1 mask 0 ...

Page 245: ...ne REI counter 0 Does not detect 0 D20 B2ECR 1 Detects occurrence of an overflow in B2 error counter 0 Does not detect 0 D19 B1ECR 1 Detects occurrence of an overflow in B1 error counter 0 Does not detect 0 D18 LREI 1 Detects Line REI 0 Does not detect 0 D17 B2E 1 Detects B2 error 0 Does not detect 0 D16 B1E 1 Detects B1 error 0 Does not detect 0 D15 D12 Reserved Reserved 0 D11 SD 1 Detects occurr...

Page 246: ...AIS STIU STIM LOF OOF LOS Bit Field Function Default D31 D26 Reserved Reserved All 0 D25 Z2M 1 Enable 0 Disable 1 D24 Z2D 1 Enable 0 Disable 1 D23 J0M 1 Enable 0 Disable 1 D22 APS 1 Enable 0 Disable 1 D21 LREICR 1 Enable 0 Disable 1 D20 B2ECR 1 Enable 0 Disable 1 D19 B1ECR 1 Enable 0 Disable 1 D18 LREI 1 Enable 0 Disable 1 D17 B2E 1 Enable 0 Disable 1 D16 B1E 1 Enable 0 Disable 1 D15 D12 Reserved ...

Page 247: ... PSBF LRDI LAIS STIU STIM LOF OOF LOS Bit Field Function Default D31 D26 Reserved Reserved All 0 D25 Z2M 1 Mask 0 Unmask 1 D24 Z2D 1 Mask 0 Unmask 1 D23 J0M 1 Mask 0 Unmask 1 D22 APS 1 Mask 0 Unmask 1 D21 LREICR 1 Mask 0 Unmask 1 D20 B2ECR 1 Mask 0 Unmask 1 D19 B1ECR 1 Mask 0 Unmask 1 D18 LREI 1 Mask 0 Unmask 1 D17 B2E 1 Mask 0 Unmask 1 D16 B1E 1 Mask 0 Unmask 1 D15 D12 Reserved Reserved All 0 D11...

Page 248: ...ects termination of SD event 0 Does not detect 0 D10 SF 1 Detects termination of SF event 0 Does not detect 0 D9 CD 1 Detects high level of CD pin input 0 Does not detect Note D8 Reserved Reserved Note D7 PSBF 1 Detects termination of PSBF event 0 Does not detect 0 D6 LRDI 1 Detects termination of Line RDI event 0 Does not detect 0 D5 LAIS 1 Detects termination of Line AIS event 0 Does not detect ...

Page 249: ... enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SD SF CD Res PSBF LRDI LAIS STIU STIM LOF OOF LOS Bit Field Function Default D31 D12 Reserved Set to 0 All 0 D11 SD 1 enable 0 disable 1 D10 SF 1 enable 0 disable 1 D9 CD 1 enable 0 disable 1 D8 Reserved Reserved 1 D7 PSBF 1 enable 0 disable 1 D6 LRDI 1 enable 0 disable 1 D5 LAIS 1 enabl...

Page 250: ...ster 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SD SF CD Res PSBF LRDI LAIS STIU STIM LOF OOF LOS Bit Field Function Default D31 D12 Reserved Reserved All 0 D11 SD 1 mask 0 unmask 1 D10 SF 1 mask 0 unmask 1 D9 CD 1 mask 0 unmask 1 D8 Reserved Set to 1 1 D7 PSBF 1 mask 0 unmask 1 D6 LRDI 1 mask 0 unmask 1 D5 LAIS 1 mask 0 unmask 1 D4 STIU...

Page 251: ...d 0 D10 SF 1 SF event in progress 0 SF event is not detected 0 D9 CD 1 The CD input is low 0 The CD input is high Note D8 Reserved Reserved Note D7 PSBF 1 PSBF event in progress 0 PSBF event is not detected 0 D6 LRDI 1 Line RDI event in progress 0 Line RDI event is not detected 0 D5 LAIS 1 Line AIS event in progress 0 Line AIS event is not detected 1 D4 STIU 1 Section TIU event in progress 0 Secti...

Page 252: ...er 0 Does not detect 0 D20 B3ECR 1 Detects occurrence of an overflow in B3 error counter 0 Does not detect 0 D19 NFJ 1 Detects Negative Frequency Justification 0 Dose not detect 0 D18 PFJ 1 Detects Positive Frequency Justification 0 Dose not detect 0 D17 PREI 1 Detects Path REI 0 Does not detect 0 D16 B3E 1 Detects B3 error 0 Does not detect 0 D15 D11 Reserved Reserved All 0 D10 PTIU 1 Detects occ...

Page 253: ...U PUNEQ PPLM ERDIP ERDIC ERDIS OPRDI PAIS LOP Bit Field Function Default D31 D25 Reserved Reserved All 0 D24 J1M 1 Enable 0 Disable 1 D23 NFJCR 1 Enable 0 Disable 1 D22 PFJCR 1 Enable 0 Disable 1 D21 PREICR 1 Enable 0 Disable 1 D20 B3ECR 1 Enable 0 Disable 1 D19 NFJ 1 Enable 0 Disable 1 D18 PFJ 1 Enable 0 Disable 1 D17 PREI 1 Enable 0 Disable 1 D16 B3E 1 Enable 0 Disable 1 D15 D11 Reserved Reserve...

Page 254: ...IU PTIM PPLU PUNEQ PPLM ERDIP ERDIC ERDIS OPRDI PAIS LOP Bit Field Function Default D31 D25 Reserved Reserved All 0 D24 J1M 1 mask 0 unmask 1 D23 NFJCR 1 mask 0 unmask 1 D22 PFJCR 1 mask 0 unmask 1 D21 PREICR 1 mask 0 unmask 1 D20 B3ECR 1 mask 0 unmask 1 D19 NFJ 1 mask 0 unmask 1 D18 PFJ 1 mask 0 unmask 1 D17 PREI 1 mask 0 unmask 1 D16 B3E 1 mask 0 unmask 1 D15 D11 Reserved Reserved All 0 D10 PTIU...

Page 255: ...U 1 Detects termination of Path TIU event 0 Does not detect 0 D9 PTIM 1 Detects termination of Path TIM event 0 Does not detect 0 D8 PPLU 1 Detects termination of Path PLU event 0 Does not detect 0 D7 PUNEQ 1 Detects termination of Path UNEQ event 0 Does not detect 0 D6 PPLM 1 Detects termination of Path PLM event 0 Does not detect 0 D5 ERDIP 1 Detects termination of Enhanced Path RDI Payload defe...

Page 256: ...clear enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PTIU PTIM PPLU PUNEQ PPLM ERDIP ERDIC ERDIS OPRDI PAIS LOP Bit Field Function Default D31 D11 Reserved Set to 0 0 D10 PTIU 1 Enable 0 Disable 1 D9 PTIM 1 Enable 0 Disable 1 D8 PPLU 1 Enable 0 Disable 1 D7 PUNEQ 1 Enable 0 Disable 1 D6 PPLM 1 Enable 0 Disable 1 D5 ERDIP 1 Enable 0 Di...

Page 257: ...register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PTIU PTIM PPLU PUNEQ PPLM ERDIP ERDIC ERDIS OPRDI PAIS LOP Bit Field Function Default D31 D11 Reserved Reserved All 0 D10 PTIU 1 Mask 0 Unmask 1 D9 PTIM 1 Mask 0 Unmask 1 D8 PPLU 1 Mask 0 Unmask 1 D7 PUNEQ 1 Mask 0 Unmask 1 D6 PPLM 1 Mask 0 Unmask 1 D5 ERDIP 1 Mask 0 Unmask 1 D4 ERDIC 1...

Page 258: ... 0 Path TIM event is not detected 0 D8 PPLU 1 Path PLU event in progress 0 Path PLU event is not detected 0 D7 PUNEQ 1 Path UNEQ event in progress 0 Path UNEQ event is not detected 0 D6 PPLM 1 Path PLM event in progress 0 Path PLM event is not detected 0 D5 ERDIP 1 Enhanced Path RDI Payload defect event in progress 0 Enhanced Path RDI Payload defect event is not detected 0 D4 ERDIC 1 Enhanced Path...

Page 259: ... of an overflow in receive FIFO overflow cell packet counter 0 Does not detect 0 D24 FEPCR 1 Detects occurrence of an overflow in receive HEC error drop cell and FCS error packet counter 0 Does not detect 0 D23 AEPCR 1 Detects occurrence of an overflow in receive HEC error correct cell and address error packet counter 0 Does not detect 0 D22 APCR 1 Detects occurrence of an overflow in receive idle...

Page 260: ...d LPCR SPCR FOPCR FEPCR AEPCR APCR VPCR LPE SPE FCSE ADRE ABOE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LCD OCD Bit Field Function Default D31 D26 Reserved Reserved All 0 D27 LPCR 1 Enable 0 Disable 1 D26 SPCR 1 Enable 0 Disable 1 D25 FOPCR 1 Enable 0 Disable 1 D24 FEPCR 1 Enable 0 Disable 1 D23 AEPCR 1 Enable 0 Disable 1 D22 APCR 1 Enable 0 Disable 1 D21 VPCR 1 Enable 0 Disable 1 D20 LPE 1 ...

Page 261: ...PCR SPCR FOPCR FEPCR AEPCR APCR VPCR LPE SPE FCSE ADRE ABOE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LCD OCD Bit Field Function Default D31 D26 Reserved Set to 0 All 0 D27 LPCR 1 Mask 0 Unmask 1 D26 SPCR 1 Mask 0 Unmask 1 D25 FOPCR 1 Mask 0 Unmask 1 D24 FEPCR 1 Mask 0 Unmask 1 D23 AEPCR 1 Mask 0 Unmask 1 D22 APCR 1 Mask 0 Unmask 1 D21 VPCR 1 Mask 0 Unmask 1 D20 LPE 1 Mask 0 Unmask 1 D19 SPE ...

Page 262: ...D Bit Field Function Default D31 D2 Reserved Reserved All 0 D1 LCD 1 Detects termination of LCD event 0 Does not detect 0 D0 OCD 1 Detects termination of OCD event 0 Does not detect 0 96 Receive ATM POS layer event termination Read clear Enable registers TAPER _RCE This register is read clear enable register of the TAPER_RC register Address Register Name Port0 Port1 Port2 Port3 Access Default Func...

Page 263: ... TAPER register Address Register Name Port0 Port1 Port2 Port3 Access Default Function TAPER_M 025C H 065C H 0A5C H 0E5C H R W 00000003 H Mask register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LCD OCD Bit Field Function Default D31 D2 Reserved Set to 0 All 0 D1 LCD 1 Mask 0 Unmask 1 D0 OCD 1 Mask 0 Unmask 1 ...

Page 264: ...ame Port0 Port1 Port2 Port3 Access Default Function SAPER 0270 H 0670 H 0A70 H 0E70 H R 00000003 H Read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LCD OCD Bit Field Function Default D31 D2 Reserved Reserved All 0 D1 LCD 1 LCD event in progress 0 LCD event is not detected 1 D0 OCD 1 OCD event in progress 0 OCD event is not detected 1...

Page 265: ...Detects that the receive function of port1 is initialized due to port reset 0 Does not detect 1 D8 P0INIR 1 Detects that the receive function of port0 is initialized due to port reset 0 Does not detect 1 D7 P3INIT 1 Detects that the transmit function of port3 is initialized due to port reset 0 Does not detect 1 D6 P2INIT 1 Detects that the transmit function of port2 is initialized due to port rese...

Page 266: ...9 8 7 6 5 4 3 2 1 0 Reserved P3INIR P2INIR P1INIR P0INIR P3INIT P2INIT P1INIT P0INIT P3BSY P2BSY P1BSY P0BSY Bit Field Function Default D31 D17 Reserved Set to 0 0 D16 IACS 1 Enable 0 Disable 1 D15 D12 Reserved Set to 0 0 D11 P3INIR 1 Enable 0 Disable 1 D10 P2INIR 1 Enable 0 Disable 1 D9 P1INIR 1 Enable 0 Disable 1 D8 P0INIR 1 Enable 0 Disable 1 D7 P3INIT 1 Enable 0 Disable 1 D6 P2INIT 1 Enable 0 ...

Page 267: ... 9 8 7 6 5 4 3 2 1 0 Reserved P3INIR P2INIR P1INIR P0INIR P3INIT P2INIT P1INIT P0INIT P3BSY P2BSY P1BSY P0BSY Bit Field Function Default D31 D17 Reserved Set to 0 0 D16 IACS 1 Mask 0 Unmask 1 D15 D12 Reserved 1 Mask 0 Unmask 1 D11 P3INIR Set to 0 0 D10 P2INIR 1 Mask 0 Unmask 1 D9 P1INIR 1 Mask 0 Unmask 1 D8 P0INIR 1 Mask 0 Unmask 1 D7 P3INIT 1 Mask 0 Unmask 1 D6 P2INIT 1 Mask 0 Unmask 1 D5 P1INIT ...

Page 268: ... receive function of port1 is completed 0 Does not detect 0 D8 P0INIR 1 Detects that the initialization of the receive function of port0 is completed 0 Does not detect 0 D7 P3INIT 1 Detects that the initialization of the transmit function of port3 is completed 0 Does not detect 0 D6 P2INIT 1 Detects that the initialization of the transmit function of port2 is completed 0 Does not detect 0 D5 P1INI...

Page 269: ...Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved P3INIR P2INIR P1INIR P0INIR P3INIT P2INIT P1INIT P0INIT P3BSY P2BSY P1BSY P0BSY Bit Field Function Default D31 D12 Reserved Set to 0 0 D11 P3INIR 1 Enable 0 Disable 1 D10 P2INIR 1 Enable 0 Disable 1 D9 P1INIR 1 Enable 0 Disable 1 D8 P0INIR 1 Enable 0 Disable 1 D7 P3INIT 1 Enable 0 Disable 1 D6 P2INIT 1 Enable 0 Disable 1 D5 P1INIT 1 Enable 0 ...

Page 270: ...erved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved P3INIR P2INIR P1INIR P0INIR P3INIT P2INIT P1INIT P0INIT P3BSY P2BSY P1BSY P0BSY Bit Field Function Default D31 D12 Reserved Set to 0 0 D11 P3INIR 1 Mask 0 Unmask 1 D10 P2INIR 1 Mask 0 Unmask 1 D9 P1INIR 1 Mask 0 Unmask 1 D8 P0INIR 1 Mask 0 Unmask 1 D7 P3INIT 1 Mask 0 Unmask 1 D6 P2INIT 1 Mask 0 Unmask 1 D5 P1INIT 1 Mask 0 Unmask 1 D4 P0INIT 1 Ma...

Page 271: ... is not under initialization 1 D8 P0INIR 1 The receive function of port0 is under initialization 0 The receive function of port0 is not under initialization 1 D7 P3INIT 1 The transmit function of port3 is under initialization 0 The transmit function of port3 is not under initialization 1 D6 P2INIT 1 The transmit function of port2 is under initialization 0 The transmit function of port2 is not unde...

Page 272: ...ter indicates the address of the illegal access Register Name Address Access Default IAADR 02A4 H R 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IAADR Bit Field Function Default D31 D13 Reserved Reserved All 0 D12 D0 IAADR Indicates the address of the illegal access 0000 H ...

Page 273: ...8 Transmit counter sampling register CSMPT This register specifies a command that saves the counter value of the performance monitoring counter to the corresponding load register Address Register Name Port0 Port1 Port2 Port3 Access Default CSMPT 02C4 H 06C4 H 0AC4 H 0EC4 H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FUPCT A...

Page 274: ... H 0AC8 H 0EC8 H R 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VPCT 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPCT 15 0 Bit Field Function Default D31 D0 VPCT Transmit valid cell packet counter 0 110 Transmit abort packet counter load register APCT POS mode This register reads the transmit abort packet counter value Address Register Name Port0 Port1 Port2 Port3 Access Default APCT...

Page 275: ...r reads the transmit FIFO underflow packet counter value Address Register Name Port0 Port1 Port2 Port3 Access Default FUPCT 02D0 H 06D0 H 0AD0 H 0ED0 H R 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FUPCT 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FUPCT 15 0 Bit Field Function Default D31 D0 FUPCT Transmit FIFO underflow packet counter 0 ...

Page 276: ... bytes counted by receive valid packet counter 1 Number of bytes 0 Number of packets 0 D4 PREICRM Selects the number of the error bits or frames counted by Path REI counter 1 Number of error frames 0 Number of error bits 0 D3 LREICRM Selects the number of the error bits or frames counted by Line REI counter 1 Number of error frames 0 Number of error bits 0 D2 B3ECRM Selects the number of the error...

Page 277: ...Indicates completion of loading POS mode 1 Loads the receive FIFO overflow packet counter 0 Indicates completion of loading 0 D10 FEPCR ATM mode 1 Loads the HEC error drop cell counter 0 Indicates completion of loading POS mode 1 Loads the receive FCS error packet counter 0 Indicates completion of loading 0 D9 AEPCR ATM mode 1 Loads the HEC error correct cell counter 0 Indicates completion of load...

Page 278: ... completion of loading 0 D3 LREICR 1 Loads the line REI counter 0 Indicates completion of loading 0 D2 B3ECR 1 Loads the B3 error counter 0 Indicates completion of loading 0 D1 B2ECR 1 Loads the B2 error counter 0 Indicates completion of loading 0 D0 B1ECR 1 Loads the B1 error counter 0 Indicates completion of loading 0 ...

Page 279: ... 20 19 18 17 16 B1ECR 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B1ECR 15 0 Bit Field Function Default D31 D0 B1ECR B1 error counter 0 115 B2 error counter load register B2ECR This register reads the B2 error counter value B2 error count is selected from the number of error bits or frames Address Register Name Port0 Port1 Port2 Port3 Access Default B2ECR 02E0 H 06E0 H 0AE0 H 0EE0 H R 00000000H 31...

Page 280: ... 19 18 17 16 B3ECR 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B3ECR 15 0 Bit Field Function Default D31 D0 B3ECR B3 error counter 0 117 Line REI counter load register LREICR This register reads the Line REI counter value Line REI count is selected from the number of error bits or frames Address Register Name Port0 Port1 Port2 Port3 Access Default LREICR 02E8 H 06E8 H 0AE8 H 0EE8 H R 00000000 H 31...

Page 281: ...7 16 PREICR 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PREICR 15 0 Bit Field Function Default D31 D0 PREICR Path REI counter 0 119 Positive Frequency Justification counter load register PFJCR This register reads the Positive Frequency Justification counter value Address Register Name Port0 Port1 Port2 Port3 Access Default PFJCR 02F0 H 06F0 H 0AF0 H 0EF0 H R 00000000H 31 30 29 28 27 26 25 24 23 22...

Page 282: ...Default D31 D16 Reserved 0 D15 D0 NFJCR Negative Frequency Justification counter 0 121 Receive valid cell packet counter load register VPCR ATM mode This register reads the receive valid cell counter value POS mode This register reads the receive valid packet counter value This count is selected from the number of valid packets or bytes for POS mode Address Register Name Port0 Port1 Port2 Port3 Ac...

Page 283: ...3 2 1 0 APCR 15 0 Bit Field Function Default D31 D0 APCR Receive idle cell and abort packet counter 0 123 Receive HEC error correct cell and address error packet counter load register AEPCR ATM mode This register reads the receive HEC error correct cell counter value POS mode This register reads the receive address error packet counter value Address Register Name Port0 Port1 Port2 Port3 Access Def...

Page 284: ...drop cell counter value POS mode This register reads the receive FCS error packet counter value Address Register Name Port0 Port1 Port2 Port3 Access Default FEPCR 0304 0704 0B04 0F04 R 00000000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FEPCR 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FEPCR 15 0 Bit Field Function Default D31 D0 FEPCR Receive HEC error drop cell and FCS error packet counter...

Page 285: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FOPCR 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FOPCR 15 0 Bit Field Function Default D31 D0 FOPCR Receive FIFO overflow cell packet counter 0 126 Receive short packet counter load register SPCR POS mode This register reads the receive short packet counter value Address Register Name Port0 Port1 Port2 Port3 Access Default SPCR 030C H 070C H 0B0C H 0...

Page 286: ...register reads the receive long packet counter value Address Register Name Port0 Port1 Port2 Port3 Access Default LPCR 0310 H 0710 H 0B10 H 0F10 H R 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LPCR 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LPCR 15 0 Bit Field Function Default D31 D0 LPCR Receive long packet counter 0 ...

Page 287: ...ets the data to be inserted at the position of the J0 byte of a transmit frame 01H 129 Transmit E1 and F1 insert register E1F1T The E1F1T register sets the transmit E1 byte Address Register Name Port0 Port1 Port2 Port3 Access Default E1F1T 0324 H 0724 H 0B24 H 0F24 H R W 00000000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F1 7 0 E1 7 0 Bit Field...

Page 288: ...W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved D3 7 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D2 7 0 D1 7 0 Bit Field Function Default D31 D24 Reserved Set to 0 0 D23 D16 D3 7 0 Sets the data to be inserted at the position of the D3 byte of a transmit frame 0 D15 D8 D2 7 0 Sets the data to be inserted at the position of the D2 byte of a transmit frame 0 D7 D0 D1 7 0 Sets the d...

Page 289: ...K1 7 0 Bit Field Function Default D31 D16 Reserved Set to 0 0 D15 D8 K2 7 0 Sets the data to be inserted at the position of the K2 byte of a transmit frame Bits 6 to 8 of the K2 byte are used when the µPD98413 transmits alarm Line AIS or Line RDI When the µPD98413 transmits alarm Line AIS or Line RDI transmission of an alarm is take precedence over the setting of K2 7 0 of this register When the µ...

Page 290: ...ion of the D5 byte of a transmit frame 0 D7 D0 D4 7 0 Sets the data to be inserted at the position of the D4 byte of a transmit frame 0 133 Transmit Line DCC insert register 2 LDCCT2 The LDCCT2 register sets the transmit D7 through D9 bytes Address Register Name Port0 Port1 Port2 Port3 Access Default LDCCT2 0334 H 0734 H 0B34 H 0F34 H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 291: ...the D11 byte of a transmit frame 0 D7 D0 D10 7 0 Sets the data to be inserted at the position of the D10 byte of a transmit frame 0 135 Transmit S1 1st Z2 and E2 insert register S1Z2E2T The S1Z2E2T register sets the transmit S1 1st Z2 and E2 byte Address Register Name Port0 Port1 Port2 Port3 Access Default S1Z2E2T 033C H 073C H 0B3C H 0F3C H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 292: ...37 Transmit G1 F2 and H4 insert register G1F2H4T The G1F2H4T register sets the transmit G1 F2 and H4 byte Address Register Name Port0 Port1 Port2 Port3 Access Default G1F2H4T 0344 H 0744 H 0B44 H 0F44 H R W 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved H4 7 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F2 7 0 Reserved G1 3 0 Bit Field Function Default D31 D24 Reserved Set to 0 0 D2...

Page 293: ...R W 00000000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved Z5 7 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z4 7 0 Z3 7 0 Bit Field Function Default D31 D24 Reserved Set to 0 0 D23 D16 Z5 7 0 Sets the data to be inserted at the position of the Z5 byte of a transmit frame 0 D15 D8 Z4 7 0 Sets the data to be inserted at the position of the Z4 byte of a transmit frame 0 D7 D0 Z3 7 0 Sets the ...

Page 294: ...res the receive J0 byte This field is updated each time a frame is received 0 140 Receive E1 and F1 drop register E1F1R The E1F1R register is used for storing the receive E1 and F1 bytes Address Register Name Port0 Port1 Port2 Port3 Access Default E1F1R 0364 H 0764 H 0B64 H 0F64 H R 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F1 7 0 E1 ...

Page 295: ...e receive D2 byte This field is updated each time a frame is received 0 D7 D0 D1 7 0 Stores the receive D1 byte This field is updated each time a frame is received 0 142 Receive K1 and K2 drop register K12R The K12R register is used for storing the receive K1 and K2 bytes Address Register Name Port0 Port1 Port2 Port3 Access Default K12R 036C H 076C H 0B6C H 0F6C H R 00000000 H 31 30 29 28 27 26 25...

Page 296: ...70 H 0F70 H R 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved D6 7 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D5 7 0 D4 7 0 Bit Field Function Default D31 D24 Reserved 0 D23 D16 D6 7 0 Stores the receive D6 byte This field is updated each time a frame is received 0 D15 D8 D5 7 0 Stores the receive D5 byte This field is updated each time a frame is received 0 D7 D0 D4 7 0 Stores th...

Page 297: ...74 H 0F74 H R 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved D9 9 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D8 7 0 D7 7 0 Bit Field Function Default D31 D24 Reserved 0 D23 D16 D9 7 0 Stores the receive D9 byte This field is updated each time a frame is received 0 D15 D8 D8 7 0 Stores the receive D8 byte This field is updated each time a frame is received 0 D7 D0 D7 7 0 Stores th...

Page 298: ... 0F78 H R 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved D12 9 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D11 7 0 D10 7 0 Bit Field Function Default D31 D24 Reserved 0 D23 D16 D12 7 0 Stores the receive D12 byte This field is updated each time a frame is received 0 D15 D8 D11 7 0 Stores the receive D11 byte This field is updated each time a frame is received 0 D7 D0 D10 7 0 Store...

Page 299: ... D15 D8 Z2F 7 0 Stores the receive 1st Z2 byte This field is updated each time a frame is received 0 D7 D0 S1 7 0 Stores the receive S1 byte This field is updated each time a frame is received 0 147 Receive 1st Z2 drop register 1 Z2FDR The Z2FDR register is used for storing the receive 1st Z2 byte Address Register Name Port0 Port1 Port2 Port3 Access Default Z2FDR 0380 H 0780 H 0B80 H 0F80 H R 0000...

Page 300: ... D0 Z2FM 7 0 Stores the receive 1st Z2 byte This field is updated when 12 contiguous frames containing the same bit 7 8 of 1st Z2 byte are received after the contents of the register are changed 0 149 Receive J1 drop register J1R The J1R register is used for storing the receive J1 byte Address Register Name Port0 Port1 Port2 Port3 Access Default J1R 0388 H 0788 H 0B88 H 0F88 H R 00000000 H 31 30 2...

Page 301: ...egister are changed 0 Note This register is updated if the same value is received in three or five time consecutive 151 Receive G1 F2 and H4 drop register G1F2H4R The G1F2H4R register is used for storing the receive G1 F2 and H4 byte Address Register Name Port0 Port1 Port2 Port3 Access Default G1F2H4R 0390 H 0790 H 0B90 H 0F90 H R 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved...

Page 302: ...4 H 0F94 H R 00000000 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved Z5 7 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z4 7 0 Z3 7 0 Bit Field Function Default D31 D24 Reserved 0 D23 D16 Z5 7 0 Stores the receive Z5 byte This field is updated each time a frame is received 0 D15 D8 Z4 7 0 Stores the receive Z4 byte This field is updated each time a frame is received 0 D7 D0 Z3 7 0 Stores the...

Page 303: ...CHAPTER 5 REGISTERS PRELIMINARY NEC confidential and Proprietary 303 MEMO ...

Page 304: ...ber of Pins PECL level pins T B D T B D ohters T B D T B D T B D T B D T B D 6 1 Features Conforms to IEEE1149 1 JTAG Boundary Scan Standard Three registers dedicated to boundary scan Instruction register Bypass register Boundary scan register Three instructions supported BYPASS instruction EXTEST instruction SAMPLE PRELOAD instruction Five pins dedicated to boundary scan JCK JTAG Clock JMS JTAG M...

Page 305: ... JMS pin at the rising edge of the clock input to the JCK pin 6 2 3 Bypass Register The bypass register consists of a one bit shift register connected between the JDI and JDO pins when the TAP controller is in Shift DR state If this register is selected while the TAP controller is in Shift DR state data is shifted to the JDO pin at the rising edge of the clock input to the JCK pin When this regist...

Page 306: ...clock input to the JCK pin and defines the operation of the TAP controller 6 3 3 JDI JTAG Data Input Pin The JDI pin is an input pin that inputs data to the JTAG boundary scan circuit register 6 3 4 JDO JTAG Data Output Pin The JDO pin is an output pin that outputs data from the JTAG boundary scan circuit This pin changes its output at the falling edge of the clock input to the JCK pin This pin is...

Page 307: ...ations of the instruction register boundary scan register and bypass register change at the rising or falling edge of the clock input to the JCK pin See Figure 6 3 Figure 6 2 State Transition of TAP Controller 1 Test Logic Reset 2 Run Test Idle 6 Shift DR 12 Shift IR 9 Exit2 DR 7 Exit1 DR 11 Capture IR 4 Select IR Scan 14 Pause IR 13 Exit IR 10 Update DR 8 Pause DR 5 Capture DR 3 Select DR Scan 16...

Page 308: ...TAP controller exits from the Test Logic Reset state the controller enters the Run Test Idle state In this state no operation is performed because the current instruction is set by the operation of the bypass register The logic operation of the JTAG boundary scan circuit is inactive even in the Select DR Scan and Select IR Scan states 2 Run Test Idle The TAP controller is in this state during scan...

Page 309: ...d the serial output direction at each rising edge of the JCK pin signal The boundary scan register or bypass register selected by the current instruction holds the previous status without change if the controller is not on the serial bus not in the Shift DR state While the controller is in this state the instruction does not change If the TAP controller is in this state at the rising edge of the J...

Page 310: ...gnal is held high at the rising edge of the JCK pin signal with the TAP controller in this state the controller enters the Select DR Scan state If the JMS signal is held low at the rising edge of the JCK pin signal the TAP controller enters the Run Test Idle state 11 Capture IR In this controller state the shift register loads the pattern of a fixed logic value 01 binary to the instruction registe...

Page 311: ...he JMS pin signal is held high at the rising edge of the JCK pin signal the TAP controller enters the Update IR state This ends the scan process If the JMS pin signal is held low at the rising edge of the JCK pin signal the TAP controller enters the Shift IR state Both the bypass register and boundary scan register selected by the current instruction retain their states without change While the TA...

Page 312: ...nd the peripheral circuit that selects a register whose contents are to be output to the JDO pin are controlled as shown in Table 6 1 The JDO pin defined in this table changes at the falling edge of the JCK pin signal after it has entered each state Table 6 1 Operation in Each Controller State Controller State Selected Register to Be Driven to JDO Pin JDO Pin Driver Test Logic Reset Run Test Idle ...

Page 313: ... c t I R S c an C a p t u r e I R S h i f t I R P a u s e I R E x i t 2 I R S h i f t I R E x i t 1 I R U p d a t e IR R u n T e s t I d l e Active B y p a s s N e w i n s t r u c t i o n O l d d a t a I n a c t i v e A c t i v e I n a c t i v e I n a c t i v e I n s t r u c t i o n r e g i s t e JDI pin signal Input data to IR IR shift register Parallel output of IR Input data to TDR TDR shift re...

Page 314: ...R E x i t 1 D R U p d a t e D R S e l e c t D R S c a n R u n T e s t I d l e T e s t L o g i c R e s e t S e l e c t I R S c a n S h i f t D R P a u s e D R S h i f t D R Active Bypas s New dat a Ol d dat a I nac t i ve Ac t i v e I n a c t i v I nac t i v e I nst r uct i on Tes t dat a r egi s t e r JCKpinsignal JMSpinsignal Controller state JDI pinsignal Input datatoIR IRshift register Parallel...

Page 315: ...troller states 2 Data is not inverted since it has been serially input to the instruction register until it is serially output 3 A fixed binary pattern data 01 with LSB Least Significant Bit being 1 is loaded to this register cell in the Capture IR controller state 4 A fixed binary pattern data 01 with LSB Least Significant Bit being 1 is loaded to this register cell in the Test Logic Reset contro...

Page 316: ...boundary scan register of serial access between the JDI and JDO instructions While this instruction is selected The states of all the signals driven from the system output pins are completely defined by the data shifted to the boundary scan register In the Update DR controller state the states of all the signals are changed only by the falling edge of the JCK pin signal The states of all the signa...

Page 317: ...CHAPTER 6 JTAG BOUNDARY SCAN PRELIMINARY NEC confidential and Proprietary 318 MEMO ...

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