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Chapter 5
Appendix
User’s Manual U17316EE1V0UM00
c19
ADD18
in
address bus signal 18
a20
ADD14
in
address bus signal 14
b20
ADD15
in
address bus signal 15
c20
GND
in
ground
a21
ADD11
in
address bus signal 11
b21
ADD12
in
address bus signal 12
c21
ADD13
in
address bus signal 13
a22
ADD8
in
address bus signal 8
b22
ADD9
in
address bus signal 9
c22
ADD10
in
address bus signal 10
a23
ADD6
in
address bus signal 6
b23
ADD7
in
address bus signal 7
c23
GND
in
ground
a24
ADD3
in
address bus signal 3
b24
ADD4
in
address bus signal 4
c24
ADD5
in
address bus signal 5
a25
n.c.
-
unconnected
b25
RDY
out
CPU Ready signal (active high, i.e. low=wait, high=ready); high
impedance while Ravin-E is not selected.
c25
ADD2
in
address bus signal 2
a26
LCS1B
in
Chip select 1 (active low)
b26
LCS0B
in
Chip select 0 (active low)
c26
GND
in
ground
a27
RDB
in
CPU read signal (active low)
b27
WRB
in
CPU write signal (active low)
c27
GND
in
ground
a28
n.c.
-
unconnected
b28
n.c.
-
unconnected
c28
n.c.
-
unconnected
a29
DAKB
in
Data acknowledge
b29
DRQB
out
Data request
c29
RDSTSB
out
Read status
a30
n.c.
-
unconnected
b30
CPUSEL
in
Select CPU interface (0=PCI, 1=asynchronous)
c30
n.c.
-
unconnected
a31
GND
in
ground
b31
PCICLK
in
PCI clock (connect to GND if asynchronous interface)
c31
GND
in
ground
a32
n.c.
-
unconnected
Table 5-2:
Host Connector CN1 (3/4)
Number
Name
Direction
Note
Description
Note: Signal direction as seen from startWARE-GHS-Ravin-E board (e.g. “in” is an input on this board and
must be driven by the main board)
Summary of Contents for startWARE-GHS-Ravin-E
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