NEC PD75402A User Manual Download Page 151

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CHAPTER 6. INTERRUPT FUNCTIONS

(4)

Pending interrupt execution

Reset

EI
EI
EI

➀

IECSI
IE0

INT0

INTCSI

RETI

➁

RETI

➀

If INT0 and INTCSI are generated simultaneously (during execution of the same instruction), INT0, which

has the higher interrupt priority, is executed first (INTCSI is held pending).

➁

When the INT0 service program is ended by the RETI instruction, the pending INTCSI service program is

started.

Summary of Contents for PD75402A

Page 1: ...USER S MANUAL µPD75402A 4 BIT SINGLE CHIP MICROCOMPUTER µPD75402A µPD75P402 Document No IEU1270C O D No IEU 644D Date Published March 1994 P Printed in Japan NEC Corporation 1989 ...

Page 2: ...hers The devices listed in this document are not suitable for use in the field where very high reliability is required including but not limited to aerospace equipment submarine cables nuclear reactor control systems and life support systems If customers intend to use NEC devices for above applications or those intend to use Standard quality grade NEC devices for the application not intended by NE...

Page 3: ...Revisions in This Version Section Description Amendment Fig 5 52 Data Transmission from Slave Device to Master Device Change Appendix B Development Tools P 117 P 179 to 181 The mark shows main revised points ...

Page 4: ...here are particular differences in functions If using it as the µPD75P402 manual the µPD75402A should be read as the µPD75P402 Checking an instruction function with a known mnemonic Appendix D Instructions Index in Alphabetical Order should be used Checking an instruction with an unknown mnemonic but with a roughly known function Check the instruction s mnemonic in 9 2 Instruction Set and Its Oper...

Page 5: ...lication Note IEA 638 75X Series Selection Guide IF 151 Operation Language Hardware Software Development Tool Related Documents Other Related Documents Note The above documents are subject to change without notice The latest documents should be used for design purposes etc Document Name Document Number Package Manual IEI 635 Surface Mount Technology Manual IEI 616 Quality Grade on NEC Semiconducto...

Page 6: ... 13 2 2 2 P20 to P23 Port 2 P30 to P33 Port 3 P50 to P53 Port 5 P60 to P63 Port 6 14 2 2 3 SCK SO SB0 SI 14 2 2 4 INT0 14 2 2 5 INT2 14 2 2 6 PCL 14 2 2 7 X1 X2 15 2 2 8 RESET Reset 15 2 2 9 VDD 15 2 2 10 VSS 15 2 3 PROM MODE 16 2 3 1 A0 to A14 Address 16 2 3 2 O0 to O7 Data 16 2 3 3 CE Chip Enable 16 2 3 4 OE Output Enable 16 2 3 5 VPP 16 2 3 6 VDD 16 2 3 7 VSS 16 2 4 PIN INPUT OUTPUT CIRCUITS 17...

Page 7: ...ration 55 5 2 3 CPU Clock Setting 59 5 2 4 Differences Between µPD75402A and µPD75402 61 5 3 CLOCK OUTPUT CIRCUIT 63 5 3 1 Clock Output Circuit Configuration 63 5 3 2 Clock Output Mode Register CLOM 64 5 3 3 Clock Output Procedure 65 5 3 4 Example of Remote Control Application 65 5 4 BASIC INTERVAL TIMER 66 5 4 1 Basic Interval Timer Configuration 66 5 4 2 Basic Interval Timer Mode register BTM 67...

Page 8: ...INSTRUCTION 156 9 4 INSTRUCTION FUNCTIONS AND APPLICATION 159 9 4 1 Move Instructions 159 9 4 2 Table Reference Instructions 162 9 4 3 Arithmetic and Logic Instructions 163 9 4 4 Accumulator Operation Instructions 165 9 4 5 Increment Decrement Instructions 166 9 4 6 Compare Instructions 167 9 4 7 Carry Flag Operation Instructions 168 9 4 8 Bit Manipulation Instructions 169 9 4 9 Branch Instruction...

Page 9: ...am 54 5 11 Processor Clock Control Register Format 56 5 12 System Clock Oscillation Circuit External Circuitry 57 5 13 Example of Poor Resonator Connection Circuit 57 5 14 Use of Variable Minimum Instruction Execution Time Function 59 5 15 Change of Φ after Power On Reset 60 5 16 Clock Generation Circuit Differences between µPD75402A and µPD75402 61 5 17 µPD75402 Processor Clock Control Register F...

Page 10: ...m Master Device to Slave Device 116 5 52 Data Transmission from Slave Device to Master Device 117 5 53 Example of Serial Bus Configuration 119 5 54 READ Command Transfer Format 121 5 55 WRITE END Command Transfer Format 121 5 56 STOP Command Transfer Format 122 5 57 STATUS Command Transfer Format 123 5 58 STATUS Command Status Format 123 5 59 RESET Command Transfer Format 124 5 60 CHGMST Command T...

Page 11: ...nterrupt Status Flag Indication Content 40 5 1 Digital Input Output Port Types and Characteristics 42 5 2 List of Input Output Pin Handling Instructions 48 5 3 Operations with Input Output Port Handling Instructions 50 5 4 Internal Pull up Resister Specification for Each Port 51 5 5 Maximum Time Required for Change of CPU Clock 60 5 6 Serial Clock Selection and Use in 3 Wire Serial I O Mode 89 5 7...

Page 12: ...lized processing The µPD75402A or 75P402 is most suitable for slave processes for the following devices such as the key input control LED etc display control or remote control send receive control etc FAX PPC Printer ECR VCR Remote control commander The µPD75P402 is a product with the µPD75402A s built in mask ROM having been replaced with the one time PROM It is compatible with the µPD75402A exce...

Page 13: ... open drain input output port LED direct drivable 4 lines Pull up resistor built in control possible by software 16 lines Pull up resistor built in control possible by mask option µPD75402A only 4 lines 1 05 MHz 524 kHz 65 5 kHz at 4 19 MHz operation Applicable to remote control output 8 bit basic interval timer Reference time generation 1 95 ms 31 3 ms at 4 19 MHz operation Watchdog timer applica...

Page 14: ...P 600 mil One time PROM µPD75P402CT 28 pin plastic shrink DIP 400 mil µPD75P402GB 3B4 44 pin plastic QFP 10mm 1 2 ORDERING INFORMATION AND QUALITY GRADE 1 Ordering Information ROM code number 2 Quality Grade Standard Please refer to Quality grade on NEC Semiconductor Devices Document number IEI 1209 published by NEC Corporation to know the specification of quality grade on the devices and its reco...

Page 15: ... and µPD75402 75P402 Item µPD75402A µPD75402 µPD75P402 ROM configuration Mask ROM One time PROM 0 95 1 91 15 3 µs 1 91 15 3 µs 0 95 1 91 15 3 µs at 4 19 MHz operation at 4 19 MHz operation at 4 19 MHz operation Designatable to be built in by mask option Not available 2 7 to 6 0 V 5 V 10 40 to 85 C 10 to 70 C 28 pin plastic DIP 600 mil 28 pin plastic shrink DIP 400 mil 44 pin plastic QFP 10 mm The ...

Page 16: ...Y 1920 8 bits ALU CY SP 5 DECODE AND CONTROL GENERAL REG RAM DATA MEMORY 64 x 4 bits PORT0 PORT1 PORT2 PORT3 PORT5 PORT6 4 4 2 4 4 4 P00 P03 P10 P12 P20 P23 P30 P33 P50 P53 P60 P63 CLOCK OUTPUT CONTROL CLOCK DIVIDER CLOCK GENERATOR STAND BY CONTROL CPU CLOCK fxx 2 PCL X1 X2 V DD VSS RESET NC VPP N ø 1 4 BLOCK DIAGRAM Remarks Parentheses for the µPD75P402 ...

Page 17: ...6 INT2 External test input X1 X2 Oscillator pin RESET Reset input VDD Power supply VSS Ground VPP Externally set to GND potential NC No connection Remarks Parentheses for the µPD75P402 If using the µPD75P402 and the printed circuit board commonly in the µPD75402A the NC pin is to be set to the GND potential VPP NC RESET P00 P01 SCK P02 SO SB0 P03 SI P50 P51 P52 P53 P30 P31 P32 VSS 1 2 3 4 5 6 7 8 ...

Page 18: ...ut CE Chip enable input OE Output enable input VDD Power supply VPP Program power supply VSS Ground VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 µ PD75P402C CT ...

Page 19: ... VDD X1 X2 NC P62 P63 P20 P21 P23 NC V SS NC P22 PCL P10 INT0 P12 INT2 P53 P52 P51 NC NC NC NC P50 P03 SI P02 SO SB0 NC 1 5 2 44 Pin Plastic QFP 10mm 1 Normal operating mode Remarks Parentheses for the µPD75P402 If using the µPD75P402 and the printed circuit board commonly in the µPD75402A the NC pin of the 30 pin corresponding to the µPD75P402 s VPP is to be set to the GND potential µPD75402AGB 3...

Page 20: ...3 O4 O5 NC A6 A7 A12 VPP NC NC NC VDD A14 A13 NC 1 2 3 4 5 6 7 8 9 10 11 23 24 25 26 27 28 29 30 31 32 33 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 O6 O7 CE NC V SS OE A9 A8 NC A10 A11 A0 A1 A2 NC NC NC NC A3 A4 A5 NC µPD75P402GB 3B4 ...

Page 21: ...402 s pin functions the 2 modes of the normal operating mode µPD75402A mode and the PROM mode are available The operating mode switches according to the VPP pin level as shown in the table below VPP Operating Mode Low level GND potential Normal operating mode High level 5 V PROM read mode High level 12 5 V PROM write verify mode PROM mode ...

Page 22: ...ible to drive the LED directly A 4 bit N ch open drain input output port Port 5 It is designatable to input output in 4 bit units It is designatable to build in the pull up resistor by mask option bit wise It is possible to drive the LED directly A 4 bit input output port Port 6 It is designatable to input output in 4 bit units It is designatable to build in the pull up resistor by software in 4 b...

Page 23: ... A serial data output pin A serial clock input output pin A serial bus input output pin A clock output pin A system clock oscillation crystal ceramic resonator connection pin If supplying the clock from the exterior input to X1 and input the inverted phase to X2 A system reset input pin Built in with the noise eliminator by analog delay A positive power supply pin A GND potential pin No Connection...

Page 24: ... input ports The status of each of Ports 0 and 1 is always inputtable irrespective of the dual function pin operation Both Ports 0 and 1 have Schmitt triggered input to prevent malfunction by noise P10 is built in with the noise eliminator by the sampling clock and P12 is built in with the noise eliminator by analog delay Ports 0 and 1 allow to designate to build in the pull up resistor respective...

Page 25: ...t Port 5 turns high level if built in with the pull up resistor or high impedance The content of the output latch turns indeterminate 2 2 3 SCK SO SB0 SI Port 0 Dual Function 3 State Input Output A serial interface input output pin It operates according to the serial operating mode register CSIM setting Each has Schmitt triggered input The serial interface stops at RESET input and each turns into ...

Page 26: ...erior a Crystal Ceramic Oscillation b External Clock 2 2 8 RESET Reset A low level active system reset input pin It has Schmitt triggered input and is built in with the noise eliminator by analog delay It has asynchronous input for RESET It accepts a signal having a certain low level width irrespective of the CPU s operation clock if one is input and system reset is effected under priority over an...

Page 27: ... 11 bits A0 to A10 A11 to A14 should be fixed to the low level 2 3 2 O0 to O7 Data Input Output An 8 bit data input output pin at PROM write verify read 2 3 3 CE Chip Enable Input A chip enable signal input pin 2 3 4 OE Output Enable Input An output enable signal input pin 2 3 5 VPP A high voltage application pin at PROM write verify It must be connected to VSS during normal operation 2 3 6 VDD A ...

Page 28: ...B C P10 INT0 B P12 INT2 B C P20 P21 P23 P22 PCL P30 to P33 E B P50 to P53 M M A P60 to P63 E B RESET B 2 4 PIN INPUT OUTPUT CIRCUITS The input output circuit of each pin is shown below in a partly simplified format Table 2 4 Pin Input output Types Pin E B Remarks A circle indicates Schmitt triggered input ...

Page 29: ...ype F A IN P U R Pull Up Resistor P U R Pull Up Resistor P U R Pull Up Resistor An input buffer of the CMOS standard Push pull output that can be turned output high impedance P ch N ch both off Schmitt triggered input having hysteresis characteristics VDD P ch IN OUT data output disable Type A Type D P U R P U R enable VDD P ch IN OUT P U R data output disable Type B Type D P U R enable ...

Page 30: ...Withstand Voltage data output disable Type F B Type M Type M A P U R Pull Up Resistor Middle High Voltage Input Buffer 10 V Withstand Voltage P U R Pull Up Resistor Middle High Voltage Input Buffer 10 V Withstand Voltage VDD P ch IN OUT P U R VDD P ch N ch data P U R enable output disable output disable N output disable P ...

Page 31: ...est mode is set and the normal operation may not be continued For example when wires from the P00 pin or RESET pin are long inter wiring noise may be added to these pins and the pin voltage may exceed VDD resulting in a misoperation Therefore wiring should be carried out so that inter wiring noise is suppressed as far as possible If it is impossible to suppress the noise noise prevention measures ...

Page 32: ...lt in with a static RAM 64 4 bits Addresses F80H to FFFH of Bank 15 are a peripheral hardware area and are built in with the input output port serial interface etc To address this data memory space of a 12 bit address the low order 8 bit address is specified directly or indirectly by an instruction The high order 4 bit address is determined by the memory bank MB to be accessed The µPD75402A is bui...

Page 33: ...B0H FBFH FF0H FFFH Table 3 1 Data Memory Configuration and Address Range in Each Addressing Mode Addressing Mode Data Memory General Register Area Not built in Stack Area mem mem bit HL Stack Addressing fmem bit Peripheral Hardware Area Memory Bank 15 Data Memory Static RAM Memory Bank 0 ...

Page 34: ...ccessed if mem 80H to FFH The address indicated by mem However Memory bank 0 is accessed if mem 00H to 3FH Memory bank 15 is accessed if mem 80H to FFH The address indicated by mem mem Even address However Memory bank 0 is accessed if mem 00H to 3EH Memory bank 15 is accessed if mem 80H to FEH The address indicated by the content of HL of Memory bank 0 If HL 00H to 3FH however The bit indicated by...

Page 35: ...he bits capable of 1 bit manipulation are limited see Table 3 2 This addressing mode is applied to the 4 instructions of the bit set and reset instructions SET1 CLR1 and testinstructions SKT SKF Example Set FLAG1 reset FLAG2 and test whether FLAG3 is 0 or not FLAG1 EQU 03FH 1 Address 3FH bit 1 FLAG2 EQU 027H 2 Address 27H bit 2 FLAG3 EQU 017H 0 Address 17H bit 0 SET1 FLAG1 FLAG 1 CLR1 FLAG2 FLAG 0...

Page 36: ... as setting the transfer data stored in the XA register pair XCH XA SIO XA SIO 4 4 bit register indirect addressing HL An addressing mode to specify the data memory space indirectly according to the content of the HL register per 4 bits The memory bank MB addressed in this addressing mode is fixed to to 0 Consequently the static RAM area of 000H to 03FH alone is addressable The peripheral hardware...

Page 37: ...ardware directly by the instruction s operand Consequently the data memory addresses to which this addressing mode is applied are FB0H to FBFH FF0H to FFFH While the 1 bit direct addressing mode mem bit is applicable only to the bit set reset test instructions this addressing mode enables multifarious bit manipulation such as the Boolean operation by the AND1 OR1 and XOR1 instructions test and res...

Page 38: ... at register save restore by the PUSH POP instruction in addition to the interrupting process subroutine process Note The Evachip packaged on the board for evaluation can address the whole area of Memory bank 0 in this addressing mode unlike in the µPD75402A To eliminate such a difference during the evaluation a value not to access beyond the range of 20H to 3FH should be set in the stack pointer ...

Page 39: ...dressing fmem bit Specify the address to be manipulated by the direct addressing mem Specify the address to be manipulated by the direct addressing mem Mem is an even address however Applicable Hardware All the hardware capable of bit manipulation IE IRQ PORTn All the hardware capable of 4 bit manipulation All the hardware capable of 8 bit manipulation Bit manipulation 4 bit manipulation 8 bit man...

Page 40: ...402A I O Map 1 2 Address 1 Bit 4 Bits 8 Bits Remarks Bit Manipula tion No of Manipulatable Addressing Hardware Name Symbol W 11 must always be written in bit 1 0 R IME Processor clock control register PCC INT0 mode register IM0 0 0 IEBT IRQBT 0 0 IECSI IRQCSI 0 0 IE0 IRQ0 0 0 IE2 IRQ2 Manipulation by EI DI instruc tion FD0H FDCH Clock output mode register CLOM Pull up resistor specify register Gro...

Page 41: ...its Remarks Bit Manipula tion No of Manipulatable Addressing Hardware Name Symbol CSIE COI WUP 0 CMDD RELD CMDT RELT SBI control register SBIC BSYE ACKD ACKE ACKT W mem bit 0 must always be written in bit 0 mem bit Bit manipulation only is possible for all the bits 11000 must always be written in the high order 5 bits Serial I O shift register SIO Slave address register SVA Port mode register Grou...

Page 42: ...t time is saved in the stack memory and then the address of each destination of branching is set in the PC Return instruction RET RETS RETI execution The content of the stack memory is set in the PC RESET input The low order 3 bits of the program memory s address 000H is set in PC10 to PC8 and the content of address 001H is set in PC7 to PC0 and then initialized It is possible to start the program...

Page 43: ...struction execution The program memory s addresses cover 000H to 77FH and the addresses shown below are assigned specially All the areas excluding 000H and 001H are available as the normal program memory Fig 4 2 Program Memory Map Address 7 6 5 4 3 0 0 0 0 H 0 0 0 0 0 0 0 1 H 0 0 2 H 0 0 0 0 0 0 0 3 H 0 0 4 H 0 0 0 0 0 0 0 5 H 0 0 8 H 0 0 0 0 0 0 0 9 H 7 7 F H Reset Start Address high order 3 bits...

Page 44: ...perate per bit by the bit manipulation instruction however In the 8 bit manipulation instruction an even address should be specified General register area Operation is possible either by the general register manipulation instruction or by the memory manipulation instruction Up to four 4 bit registers are available Of the 4 general registers that part which is not used in the program is available a...

Page 45: ...ther It is impossible to access an address to which the peripheral hardware is not assigned since the data memory is not built in See Table 3 4 µPD75402A I O Map Note The static RAM is indefinite at reset Therefore it should be initialized to zero at the beginning of the program RAM clear This must be carried out for sure to avoid unexpected bugs Example Clear all the areas 00H to 3FH of the stati...

Page 46: ...each of which is operated per 8 bits The HL register pair is available as the data pointer to indirectly address the memory The general register area can be addressed and accessed as an ordinary RAM regardless of whether it is used as a register or not Fig 4 4 General Register Configuration X A H L 0 1 H 0 0 H 0 3 H 0 2 H Remarks The figure in the lower right corner is the assigned data memory add...

Page 47: ...lators The 4 bit data process instruction is executed mainly by the A register and the 8 bit data process instruction is executed mainly by the XA register pair In the bit manipulation instruction the carry flag CY functions as the bit accumulator Fig 4 6 Accumulators CY X A Bit Accumulator 8 Bit Accumulator A 4 Bit Accumulator ...

Page 48: ...transfer instruction to determine the stack area It is impossible to read the content of the SP Zero is always written in the SP s bit 0 It is recommended to initialize by writing 40H in the SP and use the built in RAM s maximum address 03FH and beyond as the stack area The content of the SP turns indeterminate at RESET input so it must be initialized to your desired value by the program initializ...

Page 49: ...5 PC10 PC8 0 0 0 0 0 PC3 PC0 PC7 PC4 0 IST0 0 0 CY SK2 SK1 SK0 PSW PUSH Instruction CALLF Instruction Interrupt Fig 4 9 Data Restored from Stack Memory Stack Stack Stack Register Pair Low Order Register Pair High Order SP 1 SP 2 SP PC10 PC8 0 0 0 0 0 PC3 PC0 PC7 PC4 PC10 PC8 0 0 0 0 0 PC3 PC0 PC7 PC4 0 IST0 0 0 CY SK2 SK1 SK0 PSW POP Instruction RET RETS Instruction RETI Instruction SP 1 SP 2 SP S...

Page 50: ...on with carry ADDC execution The carry flag also has the function of the bit accumulator so it can perform Boolean operation with the bit address specify data memory and can store its results The carry flag is operated by a dedicated instruction irrespective of the other PSW bits The carry flag turns indeterminate with the RESET input Table 4 1 Carry Flag Manipulation Instructions Instruction Mnem...

Page 51: ...rectly by the program Table 4 2 Interrupt Status Flag Indication Content 0 Status 0 In a normal programming process Enable to accept any interrupt 1 Status 1 In an interrupting process Disable to accept any interrupt The content of IST0 is saved to the stack memory as part of the PSW if the interrupt is accepted and then set automatically to 1 and set to 0 by the RETI instruction As it is impossib...

Page 52: ...ory space All data memory handling instructions can be used on all of the ports and a wide variety of bit operations can be performed in addition to 4 bit input output Note On the µPD75402A it is not possible to perform 8 bit input output by pairing two ports Fig 5 1 Digital Input Output Port Data Memory Addresses Address 3 2 1 0 Symbol FF0H P03 P02 P01 P00 PORT0 FF1H 0 P12 0 P10 PORT1 FF2H P23 P2...

Page 53: ... PORT3 4 bit input output PORT2 PORT6 PORT5 4 bit input output N ch open drain up to 10 V Pins also function as SO SB0 SI SCK INT0 INT2 See chapter 1 Port 2 pins also function as PCL Internal pull up resistor can be specified bit by bit by mask option µPD75402A only LED direct drive capability On the µPD75402A a pull up resistor can be incorporated on chip for all port pins except pins P00 P10 On ...

Page 54: ...Elimination Circuit Input Buffer with Hysteresis Characteristics INT0 INT2 P12 INT2 P10 INT0 P ch Pull Up Resistor PO0 POGA Bit 0 VDD Output Buffer with Capability of Switching between Push Pull Output and N ch Open Drain Output P03 SI P02 SO SB0 P01 SCK P00 P ch Pull Up Resistors VDD SI SCK SO Internal SCK Selcetor CSIM PO1 POGA Bit 1 Φ ...

Page 55: ...IPHERAL HARDWARE FUNCTIONS Fig 5 3 Configuration of Port 3 Remarks n 0 to 3 Input Buffer PM 3 n 0 PM 3 n 1 M P X Output Latch PM 3 n PMGA Bit n Output Buffer POGA Bit 3 PO3 P ch Pull Up Resistor VDD P 3 n Internal Bus ...

Page 56: ...pecification is performed by bit 2 PM2 of PMGB for port 2 and by bits 4 to 7 PM60 to 63 of PMGA for port 6 Remarks m 2 or 6 Internal Bus Output Latch PM2 PM60 to 63 Input Buffer POGA Bit m POm PMm 0 PMm 1 P ch Pull up Resistors VDD P m 0 P m 1 P m 2 P m 3 Output Buffer PMGB Bit 2 PMGA bits 4 to 7 M P X ...

Page 57: ...orresponding port mode register bit is 0 and as an output port when 1 Since when output mode is selected by setting the port mode register the output latch contents are simulta neously output to the output pin the output latch contents must be overwritten in advance with the required value before output mode is set Port mode register group A and B are each set by an 8 bit memory handling instructi...

Page 58: ...tput Specification Address 7 6 5 4 3 2 1 0 Symbol FECH PM5 PM2 PMGB Port 2 P20 to P23 Input Output Specification Port 5 P50 to P53 Input Output Specification Port 6 input output specification is performed as a 4 bit unit Ensure that 0000 or 1111 is written to PMGA bits 7 through 4 5 1 3 Digital Input Output Port Handling Instructions As all the input output ports in the µPD75402A are mapped onto d...

Page 59: ... instructions All 4 bit memory handling instructions can be used such as MOV XCH ADDS and INCS in addition to the IN OUT instructions Example 1 To output accumulator contents to port 3 OUT PORT3 A 2 To add the accumulator value to the data output to port 5 and output the result MOV HL PORT5 ADDS A HL A A PORT5 NOP MOV HL A PORT5 A Table 5 2 List of Input Output Pin Handling Instructions PORT 0 POR...

Page 60: ...tput buffer remains off When an INCS instruction is executed data comprising the individual pin data 4 bit 1 is latched in the output latch The output buffer remains off When a bit wise data memory rewriting instruction such as the SET1 CLR1 SKTCLR instructions is executed the output latch for the specified bit can be rewritten as directed by the instruction but the contents of the output latches ...

Page 61: ...ut data to output latches and outputs data from pins Exchanges data between output latches and accumulator Increments output latch contents by 1 Changes output pin status as per instruction Input Mode Tests pin data Operation between pin data and CY Transfers pin data to accumula tor Transfers accumulator data to output latches Output buffer remains off Transfers pin data to accumula tor and trans...

Page 62: ...bit manipulation is not possible RESET input clears this register to zero Internal pull up resistor specification for port 3 is valid only for input pins specified as in input mode The status of pins specified as in output mode is without pull up resistor irrespective of the POGA setting Table 5 4 Internal Pull Up Resistor Specification for Each Port Port Pin Name Internal Pull Up Resistor Specifi...

Page 63: ... 8 Pull Up Resistor Incorporation Switching Timing Remarks Φo through Φ3 are internal operation timing clock pulses After pull up resistor incorporation has been specified by overwriting POGA in consideration of the external load capacity the pin level should be stabilized by execution of an NOP instruction etc before an input output instruction is executed Example To perform input after specifyin...

Page 64: ...a fetch by 1 machine cycle instruction b Data fetch by 2 machine cycle instruction c Data latching by 1 machine cycle instruction d Data latching by 2 machine cycle instruction 1 Machine Cycles Manipulation Instruction Input Timing Instruction Execution 2 Machine Cycles Manipulation Instruction Instruction Execution Input Timing Manipulation Instruction Instruction Execution Output Latch Output Pi...

Page 65: ...ssor clock control register 4 1 clock cyck fCY of Φ is 1 machine cycle of an instruction Instruction execution Internal Bus VDD X1 X2 System Clock Oscillation Circuit fXX or fX STOP Oscillation 1 2 1 16 1 16 to 1 512 Frequency Divider Selector Frequency Divider CPU INT0 Noise Eliminator Clock Output Circuit Φ HALT F F S R Q RESET Input Falling Edga Detection Signal RESET Input Rising Edge Detectio...

Page 66: ...ion of each block is described below 1 Processor clock control register PCC The PCC is a 4 bit register which performs selection of the CPU clock Φ and control of the CPU operating mode The format of the PCC is shown in Fig 5 11 When bit 3 or bit 2 is set 1 standby mode is selected When standby mode is released by the Standby Release signal both bits are automatically cleared and the normal operat...

Page 67: ...um speed selection 1 machin cycle 0 95 µs as CPU clock 3 2 1 0 Symbol FB3H PCC3 PCC2 PCC1 PCC0 PCC CPU clock selection bits when fXX 4 19 MHz When fXX 4 19 MHz CPU Clock Frequency 1 Machine Cycle 0 0 Φ Output fXX 64 65 5 kHz 15 3 µs 0 1 Setting prohibited 1 0 Φ fXX 8 524 kHz 19 1 µs 1 1 Φ fXX 4 1 05 MHz 0 95 µs When 4 19 MHz fXX 5 0 MHz When fXX 4 19 MHz CPU Clock Frequency 1 Machine Cycle 0 0 Φ O...

Page 68: ...e 2 When using the system clock generation circuit the area enclosed in dotted line in Fig 5 12 should be wired in order to avoid effects of wiring capacitance etc as shown below Minimize the length of wiring Do not cross other signal lines or position wiring close to a variable high current The connecting point of the oscillator capacitor should always be of the same potential as VDD Do not conne...

Page 69: ...esonator Connection Circuit 2 2 c Signal line close to varyin high current d Current flows an oscillator power supply line potentials at A B and C fluctuate High current X1 X2 VDD VDD µPD75402A X1 X2 A VDD VDD PORTn C B µPD75402A e Signal is picked up X1 X2 VDD µPD75402A ...

Page 70: ...d in 3 steps By using this function to select operation at high speed 0 95 µs When operating at 4 19 MHz when the power supply voltage is 5 V and low speed operation 15 3 µs When operating at 4 19 MHz in backup mode applications can be implemented in which reduced current consumption and low power operation is possible which is an extremely useful facility Fig 5 14 Use of Variable Minimum Instruct...

Page 71: ...oltage cannot be attained after a power on reset Table 5 5 Maximum Time Required for Change of CPU Clock 0010 1 0000 0011 1 0000 8 0010 15 3 µs 0011 8 0000 16 0011 0010 16 PCC Before Change PCC After Change Max No of Machine Cycles Required for Change of Φ Max Time Required for Change of Φ When fXX 4 19 MHz When standby mode is not set until Φ changes Fig 5 15 Change of Φ after Power On Reset 5V 0...

Page 72: ...ssor clock control register 4 1 clock cycle tCY of Φ is 1 machine cycle of an instruction Internal Bus VDD X1 X2 System Clock Oscillation Circuit fXX or fX STOP Oscillation 1 2 1 16 to 1 512 Frequency Divider Selector Frequency Divider CPU INT0 Noise Eliminator Clock Output Circuit HALT F F S R Q RESET Input Falling Edga Detection Signal RESET Input Rising Edge Detection Signal Standby Release Sig...

Page 73: ...in the µPD75402 switching Φ is 2 step rather than 3 step High speed mode 0 95 µs at 4 19 MHz cannot be specified 3 2 1 0 Symbol FB3H PCC3 PCC2 PCC1 0 PCC CPU clock selection bits when fXX 4 19 MHz When fXX 4 19 MHz CPU Clock Frequency 1 Machine Cycle 0 Φ Output fXX 64 65 5 kHz 15 3 µs 1 Φ fXX 8 524 kHz 19 1 µs When 4 19 MHz fXX 5 0 MHz When fXX 4 91 MHz CPU Clock Frequency 1 Machine Cycle 0 Φ Outp...

Page 74: ... configuration of the clock output circuit is shown in Fig 5 18 Fig 5 18 Clock Output Circuit Configuration Remarks When switching between clock output enabled disabled states consideration has been given to ensuring that a short pulse is not output From Clock Generation Circuit Φ fXX 2 6 Selector CLOM0 CLOM1 CLOM3 CLOM 4 0 Internal Bus P22 PCL PMGB Bit 2 Port 2 Input Output Mode Specification Bit...

Page 75: ...ET input clears CLOM to zero and selects the clock output disabled state Fig 5 19 Clock Output Mode Register Format Note Ensure that 0 is written to bit 2 of CLOM Address 3 2 1 0 Symbol FD0H CLOM3 0 CLOM1 CLOM0 CLOM Clock output frequency selection bits When fXX 4 19 MHz 0 0 Φ output 1 05 MHz 524 kHz 65 5 kHz 0 1 Setting prohibited 1 0 1 1 fXX 26 output 65 5 kHz Φ is the CPU clock selected by PCC ...

Page 76: ...OV XA 04H MOV PMGB XA PMGB 00000100B 2 To output Φ The PCL P22 pin outputs the clock from the low impedance state MOV A 0 OUT PORT2 A P22 0 MOV XA 04H MOV PMGB XA MOV A 1000B MOV CLOM A CLOM 1000B 5 3 4 Examle of Remote Control Application The µPD75402A clock output functions can be used in remote control applications The remote control output carrier frequency is selected by the clock frequency s...

Page 77: ...also be used as a watchdog timer for the detection of inadvertent program looping 5 4 1 Basic Interval Timer Configuration The configuration of the basic interval timer is shown in Fig 5 21 Fig 5 21 Basic Interval Timer Configuration From Clock Generation Circuit fxx 2 5 fxx 2 9 MPX BTM3 BTM2 1 1 4 SET1 Internal Bus 8 Basic Interval Timer 8 Bit Frequency Divider Clear Clear Set Bt Interrupt Reques...

Page 78: ...erval timer With a RESET input BTM contents are cleared to zero and the interrupt request signal generation interval is set to the maximum length Fig 5 22 Basic Interval Timer Mode Register Format Note Ensure that 1 is written to bits 1 and 0 3 2 1 0 Symbol F85H BTM3 BTM3 1 1 BTM 0 fXX 29 8 18 kHz 217 fXX 31 3 ms 1 fXX 25 131 kHz 213 fXX 19 5 ms Interrupt Interval Wait Time when Standby Mode is Re...

Page 79: ...an 8 bit handling instruction Data cannot be written to the timer Note When the basic interval timer contents are read it may happen that unstable data in the process of count updating is read To prevent this the read instruction should be executed twice then the two read contents should be compared If a comparison of the two read contents shows appropriate values the latter contents are taken as ...

Page 80: ...Next the program is divided into a number of modules whose processing should terminate within the standard time and the counter BT and interrupt request flag IRQBT are cleared each time a module ends A program is written such that an interrupt INTBT is not generated if operation is normal In other words if an interrupt is generated this is interpreted as indicating inadvertent program looping The ...

Page 81: ...ed and allows power dissipation to be reduced 2 3 wire serial I O mode In this mode 8 bit data transfer is performed using three lines The serial clock SCK serial output SO and serial input SI In the 3 wire serial I O mode simultaneous transmission and reception is possible increasing the data transfer processing speed The 3 wire serial I O mode allows connection to 75X series and 78K series devic...

Page 82: ...et device for serial communication a command which gives a directive to the target device and actual data The receiver can determine by hardware whether the received data is an address command or actual data Fig 5 23 Example of SBI System Configuration Note When the µPD75402A is used as a slave CPU its address is limited to the range C0H to C7H 5 5 2 Serial Interface Configuration The serial inter...

Page 83: ...Comparator Shift Registe SIO r Bus Release Command Ac Knowledge Detection Circuit Serial Clock Copunter Serial Clock Control Cirucit INTCSI Control Circuit Serial Clock Selector External SCK INTCSI IRQCSI Signal Setting fxx 24 Busy Ac Knowledge Output Circuit SO Latch CMDT RELT Match Signal SET CLR D Q Bit Test SBIC Bit Manipulation 8 8 8 RELD CMDD ACKD Selector ACKT ACKE BSYE ...

Page 84: ... reception operations are controlled by writes to the SIO See 5 5 3 3 Shift register for details 4 SO latch A latch which holds the SO SB0 and SI pin levels Can be directly controlled by software Set at the end of the 8th SCK pulse in the SBI mode See 5 5 3 2 Serial bus interface control register for details 5 Serial clock selector Selects the serial clock to be used 6 Serial clock counter Counts ...

Page 85: ...ock to the shift register Also controls the clock output to the SCK pin when the internal system clock is used 10 Busy acknowledge output circuit bus release command acknowledge detection circuit These circuits perform output and detection of various control signals in the SBI mode They do not operate in the 3 wire serial I O mode 5 5 3 Register Functions 1 Serial operating mode register CSIM The ...

Page 86: ...Bit W Remarks R Read only W Write only Note 0 must be written to CSIM bits 4 2 0 Serial clock selection bit W Serial Clock CSIM1 SCK Pin Mode 3 Wire Serial I O Mode SBI Mode 0 Input clock to SCK pin from off chip Input 1 fXX 24 262 kHz Output Remarks When fXX 4 19 MHz Serial interface operating mode selection bit W Shift Register Bit Order CSIM3 Operating Mode SO Pin Function SI Pin Function 0 1 3...

Page 87: ...t match When slave address register SVA and shift register data match COI A COI read is valid only before the start or after completion of a serial transfer During a transfer an indeterminate value will be read Also COI data written by an 8 bit manipulation instruction is ignored Serial interface operation enable disable specification bit W 0 IRQCSI set at end of every serial transfer in each mode...

Page 88: ...ce 1 1 Serial clock output high level output 3 The following procedure should be used to clear CSIE during a serial transfer Clear the interrupt enable flag to set the interrupt disabled state Clear CSIE Clear the interrupt request flag Example 1 This example selects fXX 24 as the serial clock generates an IRQCSI serial interrupt at the end of each serial transfer and selects the mode in which ser...

Page 89: ...instructions Read write capability differs from bit to bit see Fig 5 26 Reset input clears this register to 00H Note In the 3 wire serial I O mode only the following bits can be used Bus release trigger bit RELT SO latch setting Command trigger bit CMDT SO latch clearing Fig 5 26 Serial Bus Interface Control Register SBIC Format 1 3 Address 7 6 5 4 3 2 1 0 Symbol FE2H BSYE ACKD ACKE ACKT CMDD RELD...

Page 90: ...fter it is completed Bus release detection flag R Clearing Conditions RELD 0 Setting Condition RELD 1 When a transfer start instruction is executed When RESET is input When CSIE 0 See Fig 5 25 When SVA and SIO do not match when an address is received RELD When the bus release signal REL is de tected Command detection flag R Clearing Conditions CMDD 0 Setting Condition CMDD 1 When a transfer start ...

Page 91: ...arted When RESET is input ACKD When the acknowledge signal ACK is de tected Synchronized with rise of SCK Busy enable bit R W Example 1 To output the command signal SET1 CMDT 2 To test RELD and CMDD and perform different processing according to the type of receive data This interrupt routine is only performed when WUP 1 and there is an address match SKF RELD Test RELD BR ADRS SKT CMDD Test CMDD BR...

Page 92: ...lue of SIO is retained The shift operation stops after transmission reception of 8 bits Fig 5 27 Configuration Around Shift Register P02 SO SB0 Internal Bus Address Comparator Shift Register SIO Shift Clock N ch Open Drain Output BUSY ACK CLK SET CLR D Q SO Latch CMDT RELT SIO reading and the start of a serial transfer write are possible at the following times When the serial interface operation e...

Page 93: ...tputs to its connected slaves a slave address to select a specific slave If these two data items the slave address output from the master and the SVA value are found to match when compared by the address comparator the relevant slave is determined to have been selected At this time bit 6 COI of the serial operating mode register CSIM is set to 1 When an address is received the bus release detectio...

Page 94: ...register for full details of CSIM CSIM is manipulated by 8 bit memory manipulation instructions but bit manipulation of CSIE is also possible Manipulation is also possible using bit names Reset input clears this register to 00H The shaded area indicates bits used in the operation halted mode Serial Clock Celection Bit W Serial Interface Operating Mode Selection Bit W Wake up Function Specification...

Page 95: ...5 3 Wire Serial I O Mode Operation The 3 wire serial I O mode allows connection to the system used in the 75X series µPD7500 series 87AD series etc Communication is performed using three lines The serial clock SCK serial output SO and serial input SI Fig 5 28 Example of 3 Wire Serial I O System Configuration 3 wire serial I O 3 wire serial I O SCK Master CPU SO SI SCK SI SO Slave CPU 1 Register se...

Page 96: ...Bit W Serial Interface Operating Mode Selection Bit W Wake up Function Specification Bit w Match Signal from Address Comparator R Serial Interface Operation Enable Disable Specification Bit W Remarks R Read only W Write only Serial clock selection bit W Serial Clock CSIM1 SCK Pin Mode 3 Wire Serial I O Mode SBI Mode 0 Input clock to SCK pin from off chip Input 1 fXX 24 262 kHz Output Remarks Figue...

Page 97: ...data match Shift Register Operation Serial Clock Counter IRQCSI Flag SO SB0 SI Pins Shift operation enabled 1 CSIE Count operation Settable Function in each mode plus port 0 function A CIO read is valid only before the start of after completion of a serial transfer During a transfer an indeterminate value will be read Also COI data written by an 8 bit manipulation instruction is ignored Serial int...

Page 98: ... Symbol FE2H BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT SBIC Bus Release Trigger Bit W Command Trigger Bit w Should not used in 3 wire serial I O mode Command trigger bit CMDT The command signal CMD Trigger output control bit The SO latch is cleared 0 by setting this bit CMDT 1 after which the CMDT bit is automatically cleared 0 Remarks W Write only Bus release trigger bit W RELT The command signal R...

Page 99: ...on the rise of SCK At the end of an 8 bit transfer the operation of the shift register stops automatically and the IRQCSI interrupt request flag is set Fig 5 29 3 Wire Serial I O Mode Timing The SO pin becomes a CMOS output and outputs the SO latch status and thus the SO pin output status can be manipulated in accordance with the setting of the RELT bit and CMDT bit However manipulation should not...

Page 100: ...iming for Shift Register R W and Serial Transfer Start External SCK 0 Automatically masked at end of 8 bit data transfer Possible only when serial transfer is halted or when SCK is high Use Slave CPU fXX 24 1 Possible only when serial transfer is halted or when SCK is high Medium speed serial transfer Mode Register When serial transfer is halted means in the operation halted mode or when the seria...

Page 101: ...isable bit CSIE 1 After an 8 bit serial transfer the internal serial clock is stopped or SCK is high Note The transfer will not be started if CSIE is set to 1 after data is written into the shift register When an 8 bit transfer ends the serial transfer stops automatically and the IRQCSI interrupt request flag is set Example In the following example the data in the RAM specified by the HL register ...

Page 102: ...9 MHz Sample program MOV XA 10000010B MOV CSIM XA Transfer mode setting MOV XA TDATA TDATA is transfer data storage address MOV SIO XA Transfer data setting start of transfer Note From the second time onward the transfer can be started by setting data in SIO MOV SIO XA or XCH XA SIO SCK µPD75402A SO SB0 SCK SI In this application the µPD75402A SI pin can be used as an input port ...

Page 103: ...SI SO SB0 SCK SO SI Other Microcomputer Sample program Main routine MOV XA 80H MOV CSIM XA Serial operation stopped external clock specification MOV XA TDATA MOV SIO XA Transfer data setting start of transfer EI IECSI EI Interrupt routine MOV XA TDATA XCH XA SIO Receive data send data start of transfer MOV RDATA XA Receive data save RETI ...

Page 104: ...ther the received data is an address command or actual data This function allows the serial interface control portion of the application program to be simplified SBI functions are incorporated in a number of devices including the 75X series and 78K series 8 bit single chip microcomputers An example of a serial bus configuration when CPUs and peripheral ICs with a serial interface conforming to the...

Page 105: ...SBI functions are described below a Address command data differentiation function Identifies serial data as an address command or actual data b Chip selection by address The master performs chip selection by address transmission c Wake up function A slave can identify address reception chip selection easily by means of the wake up function settable releasable by software When the wake up function ...

Page 106: ...sfer timing is shown in Fig 5 33 Fig 5 33 SBI Transfer Timing The bus release signal and command signal are output by the master The BUSY signal is output by the slave ACK can be output by either the master or slave normally output by the 8 bit data receiver The serial clock is output by the master continuously from the start of an 8 bit data transfer until BUSY is released Address Transfer SCK SB...

Page 107: ... line has changed from high to low when the SCK line is high when the serial clock is not being output This signal is output by the master Fig 5 35 Command Signal a Bus release signal REL The bus release signal indicates that the SB0 line has changed from low to high when the SCK line is high when the serial clock is not being output This signal is output by the master Fig 5 34 Bus Release Signal ...

Page 108: ...l is defined as an address In a slave this condition is detected by hardware and a check is performed by hardware to see if the 8 bit data matches the slave s own specification number slave address If the 8 bit data matches the slave address that slave is determined to have been selected and communication is subsequently performed with the master until a disconnect directive is received from the m...

Page 109: ...ig 5 38 Command SCK SB0 Command Signal Command 1 2 3 4 5 6 7 8 C7 C6 C5 C4 C3 C2 C1 C0 Fig 5 39 Data SCK SB0 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 Data The 8 bit data following the command signal is defined as a command 8 bit data with no command signal is defined as data The way in which commands and data are used can be freely decided according to the communication specifications ...

Page 110: ...transfer Its position is arbitrary and it can be synchronized with any SCK clock cycle After 8 bit data transmission the sender checks whether the receiver has sent back an acknowledge signal If an acknowledge signal is not returned within a specific time after data transmission reception can be judged not to have been performed correctly When output in synchronization with 11th SCK clock cycke SC...

Page 111: ...gnal With the SBI a slave reports its busy status to the master by driving the SB0 line low The busy signal is output following the acknowledge signal output by the master or slave Busy signal setting release is performed in synchronization with the fall of SCK When the busy signal is released the master automatically terminates output of the SCK serial clock When the busy signal is released and t...

Page 112: ...dicates bits used in the SBI mode Address 7 6 5 4 3 2 1 0 Symbol FE0H CSIE COI WUP 0 CSIM3 0 CSIM1 0 CSIM Serial Clock Selection Bit W Serial Interface Operating Mode Selection Bit W Wake up Functing Specification Bit w Signal from Address Comparator R Serial Interface Operation Enable Disable Specification Bit W Remarks R Read only W Write only Serial clock selection bit W Serial Clock CSIM1 SCK ...

Page 113: ...essary to confirm that the SB0 pin has been driven high after BUSY is released before setting WUP 1 Signal from address comparator R Clearing Conditions COI 0 Setting Condition COI 1 When slave address register SVA and shift register data do not match COI When slave address register SVA and shift register data match A COI read is valid only before the start or after completion of a serial transfer...

Page 114: ...rigger Bit W Acknowledge Enable Bit R W Acknowledge Detection Flag R Busy Enable Bit R W Remarks R Read only W Write only R W Read write enabled Bus release trigger bit W RELT The bus release signal REL trigger output control bit The SO latch is set 1 by setting this bit RELT 1 after which the RELT bit is automatically cleared 0 Note SB0 must not be set during a serial transfer Ensure that it is s...

Page 115: ...ansfer ACK is output in synchronization with the next SCK After the ACK signal is output ACKT is automatically cleared 0 Note 1 ACKT must not be set 1 before completion of a serial tramsfer or during a transfer 2 ACKT cannot be clearedby software 3 When ACKT is set ACKE should be reset to 0 Acknowledge enable bit R W When set before end of transfer ACK is output is synchronization with the 9th SCK...

Page 116: ...ed Table 5 7 Serial Clock Selection and Use in SBI Mode When serial transfer is halted means in the operation halted mode or when the serial clock is masked after an 8 bit transfer When the internal system clock is selected SCK stops at 8 pulses internally but externally the count continues until the slave is in the ready state Serial Clock CSIM 1 Source Serial Clock Masking Possible Timing for Sh...

Page 117: ...nals are listed in Table 5 8 Fig 5 42 RELT CMDT RELD CMDD Operation Master Fig 5 43 RELT CMDT RELD CMDD Operation Slave Tramsfer Start Directive SIO SCK SB0 RELT CMDT RELD CMDD Transfer Start Directive Write to SIO SIO SCK So Latch RELT Master CMDT Master RELD CMDD When Address Matches When Address Does not Match 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ...

Page 118: ...ARDWARE FUNCTIONS Fig 5 44 ACKT Operation Note ACKT must not be set before the end of a transfer SCK SB0 ACKT When set in this interval ACK signal is output in 1 clock interval immediately after ACKT is set ACK D2 D1 D0 6 7 8 9 ...

Page 119: ...0 ACK SCK SB0 ACKE When ACKE is set in this interval and ACKE 1 on next fall of SCK ACK signal is output in 1 clock interval immediately after ACKE is set 7 8 9 D2 D1 D0 ACK 6 c When ACKE 0 on completion of transfer d When ACKE 1 interval is short SCK SCK ACKE 1 2 7 8 9 D7 D6 D2 D1 D0 ACK signal is not output When ACKE 0 at this point SCK SB0 ACKE ACK signal is not output When ACKE is set and clea...

Page 120: ...SCK SB0 ACKD 7 8 9 D2 D1 D0 ACK c Clearing timing when transfer start directive is given during busy state Transfer Start Directive Start of Transfer SIO SCK SB0 ACKD ACK D0 D2 D1 7 8 9 6 Fig 5 47 BSYE Operation SIO SCK SB0 ACKD D2 D1 D0 6 7 8 9 ACK BUSY D7 D6 Start of Transfer Transfer Start Directive SCK SB0 BSYE 6 7 8 9 D2 D1 D0 ACK BUSY When BSYE 1 at this Point When BSYE is Reset in this Inte...

Page 121: ...nabled SB0 rising edge when SCK 1 SB0 falling edge when SCK 1 Low level signal output to SB0 in 1 SCK clock intercal after serial receive comple tion Low level signal output to SB0 after Acknowledge signal High level signal output to SBO before start or after completion of serial transfer Master Master Master slave Slave Slave RELD set CMDD Cleared CMDD set ACKD set RELT set CMDT set ACKE 1 ACKE s...

Page 122: ... 7 8 SCK SCK SB0 CMD 1 2 7 8 SCK 1 SB0 2 7 8 Synchronization clock for output of address command data ACK signal Synchronous BUSY signal etc Address command data is transferred in first 8 cycles 8 bit data transferred in synchronization with SCK after REL signl and CMD signal output 8 bit data transferred in synchronization with SCK after CMD signal only is output without output of REL signal 8 bi...

Page 123: ...ata bus line output is N ch open drain an external pull up resistor is necessary Fig 5 48 Pin Configuration Diagram Note Since the N ch open drain must be turned off during data reception FFH should be written to SIO beforehand It can always be turned off during transmission However when the wake up function specification bit WUP is 1 the N ch transistor is always off and therefore FFH need not be...

Page 124: ...register of the transmitting device transmission errors can be detected in the following ways a Comparison of pre transmission and post transmission SIO data In this case a transmission error is judged to have been generated if the two data items are different b Use of slave address register SVA Transmission is performed after also setting the send data in the SVA register After transmission the C...

Page 125: ... Serial Transfer 1 2 3 4 5 6 7 8 9 ACK BUSY READY BUSY Clear ance ACKT Setting BUSY Clear ance BUSY Output ACK Output IRQCSI Gene ration When SVA SIO Serial Receive Operation CMDD Clear ance RELD Setting CMDD Setting A7 A6 A5 A4 A3 A2 A1 A0 Address Master Device Processing Transmission Side Program Processing Hardware Operation Transfer Line SCK Pin SB0 Pin Slave Device Processing Reception Side P...

Page 126: ...n BUSY Clear ance 1 2 3 4 5 6 7 8 9 C7 C6 C5 C4 C3 C2 C1 C0 Command Hardware Operation Program Processing Slave Device Processing Reception Side SB0 Pin SCK Pin Transfer Line Hardware Operation Program Processing Master Device Processing Transmission Side CMDT Setting Write to SIO Serial Transmit Operation SIO Read Command Analysis ACKT Setting BUSY Clear ance READY BUSY ACK Interrupt Servicing Pr...

Page 127: ... SB0 Pin Slave Device Processing Reception Side Program Processing Hardware Operation Serial Receive Operation Serial Transmit Operation Write to SIO 1 2 3 4 5 6 8 7 9 D7 D6 D5 D4 D3 D2 D1 D0 Data Interrupt Servicing Preparation for Next Serial Transfer IRQCSI Genera tion ACKD Setting SCK Stop page READY BUSY ACK ACKT Setting SIO Read IRQCSI Genera tion ACK Output BUSY Output BUSY Clear ance BUSY ...

Page 128: ...ardware Operation BUSY Clear ance Serial Transmit Operation IRQCSI Genera tion BUSY Output BUSY Clear ance ACKD Setting Write to SIO Write to SIO BUSY READY D7 D6 D5 D4 D3 D2 D1 D0 Data 1 2 3 4 5 6 7 8 9 ACK BUSY READY D7 D6 1 2 IRQCSI Genera tion ACK Output Serial Reception Receive Data Processing Serial Receive Operation ACKT Setting SIO Read FFH Write to SIO SCK Stop page Slave Device Processin...

Page 129: ...owing example the data in the RAM specified by the HL register is transferred to SIO and at the same time the SIO data is fetched into the accumulator and the serial transfer is started MOV XA HL Fetch send data from RAM XCH XA SIO Exchange send data with receive data and start transfer 11 Points to note concerning SBI mode a Detection of the slave selected nonselected state is performed by detect...

Page 130: ...command a Serial bus configuration In the serial bus configuration in the application examples given here the µPD75402A is connected to the bus line as one of the devices on the serial bus The µPD75402A uses two pins The serial data bus SB0 P02 SO and the serial clock SCK P01 An example of the serial bus configuration is shown in Fig 5 53 Only addresses C0H through C7H can be allocated to the µPD7...

Page 131: ...ion by transmitting the address of the slave to be communicated with and selecting the slave chip selection When the slave receives the address it communicates with the master by returning ACK The slave changes from non selected to selected status Communication is performed between the slave selected by the processing in and the master by the transfer of commands and data However as command and da...

Page 132: ...rite data length is variable between 1 and 256 bytes and is specified as a parameter by the master If 00H is specified as the data length this is interpreted as a 256 byte data transfer specification Fig 5 55 WRITE END Command Transfer Format iii Command formats The transfer format of each command is shown below READ command This command performs a read from the slave The read data length is varia...

Page 133: ...ore the reception of all the data In this case the data up to the reception of the END command is valid When data is transmitted the master compares the SIO contents before and after the transmission to check whether the data was correctly output onto the bus If the SIO contents before and after the transmission are different the master suspends data transmission by sending a STOP command Fig 5 56...

Page 134: ... Bit indicating possibility of data transmission 0 No data for transmission 1 1 or more bytes of send data ready Bit indicating possibility of data reception 0 No receive data storage area 1 1 or more bytes of receive data storage area ready Bit indicating error occurrence 0 No error 1 Error occurred in previous transfer Bit indicatin possibility of change of master 0 Chang of master not possible ...

Page 135: ...and Transfer Format M S CHGMST ACK Command S S Data ACK Data Remarks M Output by master S Output by slave When a slave receives the CHGMST command it determines whether it can assume mastership and returns data to the master This data is as follows 0FFH Change of master possible 00H Change of master not possible When the slave sends this data it compares the SIO contents before and after transmiss...

Page 136: ...5 61 Master and Slave Operations after an Error Errors are generated in the following circumstances Errors generated on the slave side If the command transfer format is wrong If an undefined command is received If the transferred data length is insufficient in a READ command If the data storage area is too small in a WRITE command If the data changes in a READ STATUS or CHGMST command data transmi...

Page 137: ...master enable flag IME and the interrupt enable flag IE b Any desired interrupt service start address can be set using the vector table for rapid starting of the actual interrupt service program c Interrupt request flag IRQ can be tested and cleared allowing checking of interrupt generation by software d Standby mode HALT can be released by an interrupt request release source is selectable from ot...

Page 138: ...Noise Elimination Circuit Analog Delay Noise Elimination Circuit Rising Edge Detection Circuit INT0 P10 INT2 P12 INTCSI INT BT Edge Detection Circuit IRQBT IRQ0 IRQCSI IRQ2 Interrupt Enable Flag IE VRQ2 VRQ1 VRQ3 Priority Control Circuit Vector Table Address Generation Circuit Standby Release Signal IST0 Decoder IME ...

Page 139: ...n the same way as an interrupt source but no vectored interrupt is generated Fig 6 2 Interrupt Vector Table 0 0 0 8 H 0 0 0 0 0 INTCSI start address high order 3 bits INTCSI start address low order 8 bits 0 0 0 2 H 0 0 0 0 0 INTBT start address high order 3 bits INTBT start address low order 8 bits 0 0 0 4 H 0 0 0 0 0 INT0 start address high order 3 bits INT0 start address low order 8 bits Address...

Page 140: ...is generated This signal is also used to release standby mode HALT mode with the exception of VRQ2 The interrupt request flags and interrupt enable flags are manipulated by bit handling instructions and 4 bit memory handling instructions In addition the interrupt enable flags are manipulated by the EI IE instruction and the DI IE instruction The SKTCLR is normally used for interrupt request flag t...

Page 141: ...ising Edge Detection Circuit Φ IM01 IM00 IM03 2 INT0 IRQ0 Setting Signal INT2 IRQ2 Setting Signal INT0 functions as an external interrupt input on which sampling clock noise elimination and detected edge selection can be performed The INT0 noise elimination circuit detects a change in level in 2 sampling clock pulses Therefore pulses narrower than the width of the 2 cycles 2tCY or 128 fXX of sampl...

Page 142: ... externally testable input which sets a testable flag on detection of a rising edge Noise elimination by the sampling clock is not performed but as there is a function for eliminating pulses which are narrower than the analog delay a signal of adequate width must be input as in the case of INT0 see Fig 6 5 Fig 6 5 INT2 Input Noise Elimination Analog Delay Analog Delay INT2 Input Eliminated as Nois...

Page 143: ...be cleared after the elapse of 16 machine cycles following the mode register modification 3 Interrupt master enable flag IME The interrupt master enable flag specifies acknowledgment enabled disabled for all interrupts IME is manipulated by the EI DI instructions With a RESET input IME is cleared to 0 and acknowledgment of all interrupts is disabled Fig 6 7 IME Format Interrupt master enable flag ...

Page 144: ...to write 0 to IST in the interrupt service routine which would result in multiple interrupt After being saved to stack memory together with the rest of the PSW when an interrupt is acknowledged IST0 is automatically set to 1 When an RETI instruction is executed the original IST0 value 0 is restored A RESET input clears 0 the flag contents Table 6 3 IST0 Interrupt Servicing Status Executing Process...

Page 145: ...O NO NO IRQxxx set YES Corresponding VRQn generation YES YES IST0 0 IME 1 Save PC and PSW contents to stack memory place data in vector table corresponding to initiated VRQn into PC Change IST0 contents to 1 Reset 0 acknowledged IRQxxx Branch to start address of interrupt service program proccessing Hold pending until IExxx is set Hold pending until IME is set Hold pending until end of processing ...

Page 146: ...ng 3 machine cycles D Execution of interrupt routine Remarks 1 An interrupt control instruction is an instruction which manipulates interrupt related hardware data memory FB H address These instructions comprise the DI and EI instructions 2 The 3 machine cycles of interrupt servicing include the time for manipulation of the stack on acknowledgment of an interrupt etc Note 1 If there are a number o...

Page 147: ...f interrupt routine Note If the next instruction is an interrupt control instruction the interrupt routine program is executed after 3 machine cycles of interrupt servicing have been performed following execution of the instruction which follows the last interrupt control instruction executed Also if the interrupt control instruction executed after IRQn is set is a DI instruction the interrupt req...

Page 148: ...truction Return from the interrupt service program is by means of an RETI instruction 1 Interrupt enabling disabling Reset EI IE0 EI IECSI EI DI IE0 DI INT0 INTCSI enabled INTCSI enabled Interrupts disabled Interrupts disabled Main Program All interrupts disabled by RESET input Interrupt enable flag set by EI IE instruction At this stage all interrupts are still disabled Interrupt master enable fl...

Page 149: ...BE 0 Status 0 Status 1 Status 0 Main Program All interrupts disabled and status 0 set by RESET input INT0 set to falling edge active Interrupts enabled by EI and EI IE instructions On fall of INT0 INT0 interrupt service program is started status is changed to 1 and all interrupts are disabled RETI instruction effects return from interrupt restores status to 0 and enables interrupts 4 ...

Page 150: ...ETI INTCSI Service Program EI IE0 INT0 Main program EI EI IECSI Although INT0 is set in the interrupt disabled state the interrupt flag is held pending The INT0 service program is started at point at which interrupts are enabled by the EI instruction Same as The INTCSI service routine is started at the point at which the pending INTCSI is enabled 4 ...

Page 151: ...Service Program INT0 Service Program Main Program If INT0 and INTCSI are generated simultaneously during execution of the same instruction INT0 which has the higher interrupt priority is executed first INTCSI is held pending When the INT0 service program is ended by the RETI instruction the pending INTCSI service program is started ...

Page 152: ...desiring to perform intermittent operation such as timer operation The HALT mode is reset by RESET input or interrupt request In either mode the contents of the registers flags and data memory immediately before setting to the standby mode are retained Because the states of the I O port output latch and the output buffer are retained the state of the I O ports is preprocessed so that the current d...

Page 153: ... change the CPU clock has elapsed after the PCC is rewritten In the standby mode the data of the general register flags mode registers output latch and all the other registers which stop operating in the standby mode and the data memory is retained Notes are given below Note 1 When the STOP mode is set the X1 pin is shorted internally to VSS GND potential to suppress clock oscillator leakage There...

Page 154: ...s unstable Therefore provide an oscillation stabilization time by making the RESET input low level sufficiently wide When the reset state is released the program branches to the reset start address This is different from normal reset operation because the contents of data memory before STOP mode setting are retained 2 HALT mode reset by RESET input When the RESET input drops from high to low the H...

Page 155: ...Instruction RESET Input Operating Mode Clock Oscillation STOP Mode Oscillation Stopped HALT Mode Oscillation Operating Mode Oscillation Stabilization Time c HALT mode reset by interrupt generation HALT Instruction Operating Mode HALT Mode Operating Mode Oscillation Standby Rlease Signal 2 Instructions Execution Clock Remarks The broken line is for the case when an interrupt request that reset the ...

Page 156: ...se a vector interrupt is not generated when the HALT mode was reset by INT2 testable input the same processing as a is performed 7 4 STANDBY MODE APPLICATION When using the standby mode proceed as follows Power interruption or other standby mode setting cause detection by interrupt input or port input I O port processing Process for minimum current drain In particular do not leave the input port o...

Page 157: ... register as required in the program The RESET pin is a Schmitt triggered input with hysteresis characteristics at the threshold level To prevent misoperation by noise a function which rejects narrow band noise by analog delay is also provided on the chip see Fig 8 1 For reset operation at power on provide an ample oscillation stabilization time from power on to reset signal acceptance as shown in...

Page 158: ...d Undefined Undefined 0 Undefined 0 0 Undefined 0 0 Reset 0 0 0 0 OFF Clear 0 0 0 Input On chip pull up resistor High level Open drain High impedance Carry flag CY Skip flag SK0 to SK2 Interrupt status flag IST0 Stack pointer SP Data Memory RAM General register X A H L Basic interval timer Serial interface Clock generator clock output circuit Counter BT Mode register BTM Shift register SIO Operati...

Page 159: ...and has the following features 1 Multipurpose bit manipulation instruction 2 Efficient 4 bit manipulation instruction 3 8 bit data transfer instruction 4 Stack instructions and base correction instructions with increase program efficiency 5 Table reference instructions suitable for continuous reference 6 1 byte relative branch instruction 7 Easy to understand NEC standard mnemonics For the address...

Page 160: ...O port operation can be performed very efficiently 9 1 2 Stack Instructions The following two kinds of stack instructions are available with the µPD75402A a MOV A n4 or MOV XA n8 b MOV HL n8 Stack signifies that these two kinds of instructions are placed in contiguous addresses Example A0 MOV A 0 A1 MOV A 1 XA7 MOV XA 07 When stack instructions are stacked such as in the example above when the add...

Page 161: ...execution of the ADDC A HL instruction the following ADDS A n4 instruction is skipped If carry is not output the ADDS A n4 instruction is executed At this time this instruction skip function is disabled and the next instruction is not skipped even if carry is output as the result of addition Therefore the program can continue after the ADDS A n4 instruction Example Decimal add accumulator and memo...

Page 162: ...ssing Modes at Peripheral Hardware Operation and Table 3 4 µPD75402A I O Map for details Identifier Description reg X A H L reg1 X H L rp XA HL n4 4 bit immediate data or label n8 8 bit immediate data or label mem 8 bit immediate data or label bit 2 bit immediate data or label fmem FB0H to FBFH FF0H to FFFH immediate data or label addr 11 bit immediate data or label caddr 11 bit immediate data or ...

Page 163: ... 77FH Remarks 1 MB is the accessible memory bank 2 4 to 7 are the addressable areas 4 Description of machine cycle field S is the number of machine cycles required when the skip operation is performed by an instruction with skip The value of S changes as follows Do not skip next instruction S 0 Skip next instruction S 1 One machine cycle equals one cycle of CPU clock Φ Three times can be selected ...

Page 164: ...A HL 1 XOR A HL 1 1 A A HL 1 RORC A 1 1 CY A0 A3 CY An 1 An NOT A 2 2 A A reg 1 1 S reg reg 1 reg 0 mem 2 2 S mem mem 1 2 mem 0 DECS reg 1 1 S reg reg 1 reg FH reg n 4 2 2 S Skip if reg n 4 reg n4 A HL 1 1 S Skip if A HL 1 A HL SET 1 CY 1 1 CY 1 CLR 1 CY 1 1 CY 0 SKT CY 1 1 S Skip if CY 1 CY 1 NOT 1 CY 1 1 CY CY Operation Skip Condition Addressing Area XCH Note 1 Instruction Group 2 Accumulator op...

Page 165: ...dr 1 2 PC 10 0 addr 5 BRCB caddr 2 2 PC 10 0 caddr 6 SP 4 SP 1 SP 2 0 PC 10 0 CALLF faddr 2 2 SP 3 0000 7 PC 10 0 faddr SP SP 4 PC 10 0 SP SP 3 SP 2 SP SP 4 PC 10 0 SP SP 3 SP 2 RETS 1 3 S SP SP 4 None then skip unconditionally PC 10 0 SP SP 3 SP 2 RETI 1 3 PSW SP 4 SP 5 SP SP 6 PUSH rp 1 1 SP 1 SP 2 rp SP SP 2 POP rp 1 1 rp SP 1 SP SP SP 2 2 2 IME IPS 3 1 IE 2 2 IE 1 2 2 IME IPS 3 0 IE 2 2 IE 0 S...

Page 166: ...RTn A 2 2 PORTn A n 2 3 5 6 HALT 2 2 Set HALT Mode PCC 2 1 STOP 2 2 Set STOP Mode PCC 3 1 NOP 1 1 No Operation Operation Bytes Skip Condition Addressing Area Machine Cycle Note 1 Instruction Group 2 I O instructions Mnemonic Operand Note 1 Note 2 CPU control instructions ...

Page 167: ...s distance with branch address 2 to 16 1 Sn Immediate data for one s complement of relative address distance with branch address 15 to 1 2 Bit manipulation addressing operation code bit addr of the second byte of the operation code of an instruction with fmem bit at the operands is shown below bit addr Accessible bits 1 0 B1 B0 F3 F2 F1 F0 Operable bits of FB0H to FBFH 1 1 B1 B0 F3 F2 F1 F0 Operab...

Page 168: ...1 0 0 0 0 R1 R0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 R1 R0 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 0 I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0 0 1 0 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 I7 I6 I5 I4 0 0 R1 R0 Mnemonic Operand Note 2 Not...

Page 169: ... 0 0 0 0 0 A3 A2 A1 A0 1 1 1 1 S3 S2 S1 S0 0 1 0 1 0 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 0 0 1 0 P1 1 0 1 0 0 1 0 P1 0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 bit addr D7 D6 D5 D4 D3 D2 D1 D0 bit addr D7 D6 D5 D4 D3 D2 D1 D0 bit addr D7 D6 D5 D4 ...

Page 170: ... A1 MOV A 1 A2 MOV A 2 OUT PORT 3 A MOV rp n8 Function rp n8 n8 I7 to I0 00H to FFH Moves 8 bit immediate data n8 to register pair rp XA HL This instruction has a stacking effect There are two stacking effects Group A MOV A n4 instruction and MOV XA n8 instruction and group B MOV HL n8 instruction When instructions of the same group are placed consecutively the stack instructions after the execute...

Page 171: ... immediate data mem to the A register and the contents of the next address to the X register mem can specify even addresses Application example Move the data of addresses 20H and 21H to register pair XA MOV XA 20H MOV mem A Function mem A mem D7 to D0 00H to 3FH Move the contents of the A register to the data memory addressed by 8 bit immediate data mem MOV mem XA Function mem A mem 1 X mem D7 to ...

Page 172: ... L L 1 BR LOOP XCH A mem Function A mem mem D7 to D0 00H to 3FH Exchanges the contents of the A register and the data memory contents addressed by 8 bit immediate data mem XCH XA mem Function A mem X mem 1 mem D7 to D0 00H to 3EH Exchanges the contents of the A register and the data memory contents addressed by 8 bit immediate data mem and exchanges the contents of the X register and the contents ...

Page 173: ... pseudo instruction DB instruction The program counter is not affected by execution of this instruction This instruction is effective when referencing table data consecutively Program Memory 7 4 3 0 Table Data H Table Data L 3 0 3 0 X X 7 4 12 8 X 3 0 PC 12 8 3 0 A 3 0 Table Address Note The MOVT XA PCXA instruction usually references the table data of the page containing the instruction However w...

Page 174: ...flag is not affected ADDC A HL Function A CY A HL CY Binary adds the data memory contents addressed by register pair HL to the contents of the A register including the carry flag If a carry is generated the carry flag is set If a carry is not generated the carry flag is reset When an ADDS A n4 instruction is placed after this instruction when a carry is generated at this instruction the ADDS A n4 ...

Page 175: ... A register and the data memory contents addressed by register pair HL and sets the result into the A register XOR A HL Function A A HL Exclusive ORs the contents of the A register and the data memory contents addressed by register pair HL and sets the result into the A register ...

Page 176: ... An A3 CY n 1 to 3 Rotates the contents of the A register 4 bit accumulator including the carry flag to the right one bit at a time 0 0 1 0 1 1 0 0 1 0 CY 3 2 1 0 A RORC A Before Execution After Execution NOT A Function A A Takes the one s complement inverts each bit of the A register 4 bit accumulator ...

Page 177: ... next instruction INCS mem Functions mem mem 1 Skip if mem 0 mem D7 to D0 00H to FFH Increments the data memory contents addressed by 8 bit immediate data mem When the data memory contents become 0 as a result of incrementing skips the next instruction DECS reg Function reg reg 1 Skip if reg FH Decrements the contents of register reg X A H L When the contents of register reg become FH as a result ...

Page 178: ...ip if reg n4 n4 I3 to I0 0 to FH If the contents of register reg X A H L equal 4 bit immediate data n4 skips the next instruction SKE A HL Function Skip if A HL If the contents of the A register and the data memory contents addressed by register pair HL skips the next instruction ...

Page 179: ...T1 CY Function CY 1 Sets the carry flag CLR1 CY Function CY 0 Clears the carry flag SKT CY Function Skip if CY 1 When the carry flag is 1 skips the next instruction NOT1 CY Function CY CY Inverts the carry flag If the carry flag is 0 it becomes 1 and if it is 1 it becomes 0 ...

Page 180: ...H to 3FH bit B1 to B0 0 to 3 Clears the bit specified by 2 bit immediate data bit of the address specified by 8 bit immediate data mem CLR1 fmem bit Function bit specified by operand 0 Clears the data memory bit specified by bit manipulation addressing fmem bit SKT mem bit Function Skip if mem bit 1 mem D7 to D0 00H to 3FH bit B1 to B0 0 to 3 If 2 bit immediate data bit of the address specified by...

Page 181: ...ddressing fmem bit is 1 skips the next instruction and clears that bit to 0 AND1 CY fmem bit Function CY CY bit specified by operand ADDs the contents of the carry flag and the contents of the data memory bit specified by bit manipulation addressing fmem bit and sets the result into the carry flag OR1 CY fmem bit Function CY CY bit specified by operand ORs the contents of the carry flag and the co...

Page 182: ...lly replaces this instruction with the optimum instruction from among the BRCB caddr and BR addr instructions BR addr Function PC addr addr PC 15 to PC 1 PC 2 to PC 16 This is a relative branch instruction with a branch range of 15 to 1 and 2 to 16 from the current address Page boundary and block boundary are not affected BRCB caddr Function PC10 to PC0 caddr caddr A10 to A0 000H to 77FH Branches ...

Page 183: ...o PC4 SP 3 SP SP 4 Restores the contents of the data memory stack addressed by the stack pointer SP to the program counter PC then increments the contents of the SP RETS Function PC10 to PC8 SP PC3 to PC0 SP 2 PC7 to PC4 SP 3 SP SP 4 Then skip unconditionally Restores the contents of the data memory stack addressed by the stack pointer SP to the program counter PC and increments the contents of th...

Page 184: ...ter pair is saved to the stack addressed by SP 1 and the low order side rpL A L is saved to the stack addressed by SP 2 POP rp Function rpL SP rpH SP 1 SP SP 2 Restores the contents of the data memory stack addressed by the stack pointer SP to register pair rp XA HL then increments the SP The contents of SP are restored to the low order side rpL A L of the register pair and the contents of SP 1 ar...

Page 185: ...determined by each interrupt enable flag EI IEXXX Function IE 1 N2 to N0 Sets the interrupt enable flag IE 1 and enables the interrupt BT CSI 0 2 DI Function IME 0 Resets the interrupt master enable flag and disables interrupts regardless of the contents of each interrupt enable flag DI IEXXX Function IE 0 N2 to N0 Resets the interrupt enable flag IE 0 and disables the interrupt BT CSI 0 2 ...

Page 186: ...o 3 5 6 to the A register Note Only 0 to 3 5 or 6 can be specified at n Output latch data output mode or pin data input mode is fetched according to input output mode specification OUT PORTn A Function PORTn A n N3 to N0 2 3 5 6 Transfers the contents of the A register to the output latch of the port specified by PORTn n 2 3 5 6 Note Only 2 3 5 or 6 can be specified at n ...

Page 187: ... control register Note The instruction following the HALT instruction is made an NOP instruction STOP Function PCC 3 1 Sets the STOP mode This instruction sets bit 3 of the processor clock control register Note The instruction following the STOP instruction is made an NOP instruction NOP Function Expend one machine cycle without performing any operation ...

Page 188: ...tructions even though they can be executed on the EVAKIT do not use them Mnemonic Operands Mnemonic Operands MOV A reg ADDC rp 1 XA A rpa XA rp reg1 A A reg reg1 n4 reg A rp 1 XA XA HL XA rp HL XA XA HL SUBS SUBC A HL HL XA rp 1 XA XCH A rpa XA rp HL mem A reg XA HL reg A XA rp XA HL MOVT XA PCDE HL XA XA BCDE AND OR XOR A n4 XA BCXA rp 1 XA MOV1 CY fmem bit XA rp CY pmem L mem A CY H mem bit A re...

Page 189: ...SKF SKT SKTCLR H mem bit AND1 OR1 CY pmem L CY H mem bit CY fmem bit CY pmem L CY H mem bit XOR1 CY pmem L CY H mem bit Mnemonic Operands NOT1 fmem bit pmem L H mem bit BR addr PCDE PCXA BCDE BCXA CALL addr PUSH BS POP BS IN XA PORTn OUT PORTn XA SEL MBn RBn GETI taddr reg X A B C D E H L rp XA BC DE HL rp XA BC DE HL XA BC DE HL rpa HL HL DE DL ...

Page 190: ...r It can program typical 256K bit to 4M bit PROMs PA 75P402CT PROM programmer adapter for µPD75P402C CT GB used connected to the PG 1500 PA 75P402GB PA 75P402CT For µPD75P402C CT PA 75P402GB For µPD75P402GB PG 1500 controller Connects PG 1500 and host machine via a serial and parallel interface and controls the PG 1500 on the host f machine Host Machine Ordering Code Product Name Supply Medium OS ...

Page 191: ...d and emulation probe Connected with a host machine and PROM programmer the IE 75001 R can perform efficient debugging EP 75402C R µPD75402AC 75402ACT emulation probe Used connected with the IE 75000 R IE 75001 R or IE 75000 R EM EP 75402GB R µPD75402AGB emulation probe Used connected with the IE 75000 R IE 75001 R or IE 75000 R EM Provided with the EV 9200G 44 44 pin conversion socket which facil...

Page 192: ...e PC 9800 Series IBM PC AT Symbolic Debugging Capability Centronics I F IE Control Program PG 1500 Controller RS 232 C Relocatable Assembler In Circuit Emulator IE 75000 R IE 75001 R IE 75000 R EM 1 PROM Programmer PG 1500 Programmer Adapter PA 75P402CT PA 75P402GB PD75P402C CT GB µ On chip PROM Products 2 EP 75402C R EP 75402GB R Emulation Probe Target System ...

Page 193: ...inch IBM format floppy disk When ordered with UV EPROM please prepare three UV EPROMs with the same contents Send the mask options data filled in the mask option information documents Preparation of the necessary documents When ordering the mask ROM please fill in the following documents Mask type ROM order form Mask type ROM order check sheet Mask option information documents Send the medium prep...

Page 194: ... XA PCXA Instruction Page Instruction Page NOP NOT A NOT1 CY OR A HL OR1 CY fmem bit OUT PORTn A POP rp PUSH rp RET RETI RETS RORC A SET1 CY SET1 fmem bit SET1 mem bit SKE A H SKE reg n4 SKF fmem bit SKF mem bit SKT CY SKT fmem bit SKT mem bit SKTCLR fmem bit STOP XCH A HL XCH A mem XCH A reg1 XCH XA mem XOR A HL XOR1 CY fmem bit 163 163 163 163 170 171 171 171 172 168 169 169 166 174 174 174 174 ...

Page 195: ... bit ACKD Acknowledge detect flag ACKE Acknowledge enable flag ACKT Acknowledge trigger bit BSYE Sync busy enable bit BT Basic interval timer BTM Basic interval timer mode register CLOM Clock output mode register CMDD Command detect flag CMDT Command trigger bit COI Address comparator coincidence signal CSIE Serial interface operation enable disable specification bit CSIM Serial operating mode reg...

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