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Operating Precautions for V

R

4133 

TM

 

 
No. 7 

Disconnect at the end of PCI burst cycle 
(Specification change notice) 

Details 

The last transfer of a PCI burst cycle is regarded as a disconnect cycle by VR4133, if STOP# and 
TRDY# are both asserted during the last-but-one data cycle, as shown in the following figure: 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

D0 ,D1,D2 are burst data; D3 is last burst data and D2 is last-but-one burst data. 
TRDY# and IRDY# are both asserted during D2 and D3. So data transfer of D2 and D3 
is finished. But because of this restriction, VR4133 mis-interpreting data phase as if it is 
disconnected at D2. Therefore D3 cycle is performed again. 

Therefore one of the following workarounds must be implemented: 

(1)  Do not use PCI-DMA function. 
(2)  Do not use LD and SD instructions and do not locate PCI memory and I/O areas in 

cached memory region of the CPU, so that burst cycles as shown above are not 
generated. 

 

PCLK 

 

 

 

AD

 

 

 

 

 

FRAME#
 

 

IRDY#

 

 

 

 

 

TRDY#

 

 

 

 

 

STOP#
 

 

 

 

 

 

 

 

mis-understanding as disconnect 

D1

 

D0

 

A

 

+0

 

 

 

 

 

unnecessary 

cycle

 

D

 

3

 

 

 

A+12

 

D3

 

D2

 

A+8

 

 
 
No. 8 

Ethernet: receive short packet 
 (Documentation errata) 

Details 

The packet size of VLAN is designed for minimum 68 bytes length, but this is not described in 
user’s manual. 
If a VLAN packet is received with a length of 64-67-byte (less than 68 byte), VR4133 will be 
judged it as a short packet, and a packet will be discarded. 

 

Using a packet with a length of less than 68 bytes can be realized by the following method: 
 
Set a ‘special value’ into VLTP (15:0) of VLTP0/1 (0x0f001464 / 0x0f001764) register. The 
‘special value' has not to be a VLAN type, which you want to receive. The data can be received 
as a usual packet, and judged as a VLAN packet by software. In this case, following items are 
different from usual VLAN procedure. 
 

(1) 

All the VLAN packets recognized by the TYPE field of receiving descriptor status are 
described as normal packets. 

(2) 

The statistics counter R64C0/1, R127C0/1, R255C0/1, R511C0/1, R1KC 0/1 and 
RMAXC0/1 count normal packets. 

 

Customer Notification  

Summary of Contents for PD30133F3-266-GA3-A

Page 1: ...Customer Notification VR4133TM 64 bit Microprocessor Operating Precautions µPD30133F3 266 GA3 A Document No TPS HE B 6009 4 Date Published June 2004 NEC Electronics Europe GmbH ...

Page 2: ...y or injury including death to persons arising from defects and or errors in PRODUCT S the customer must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features The customer agrees to indemnify NEC against and hold NEC harmless from any and all consequences of any and all claims suits actions or demands asserted against NEC made by a thi...

Page 3: ...Table of Contents A Table of Operating Precautions 4 B Description of Operating Precautions 5 C Valid Specification 10 D Revision History 11 Customer Notification 3 ...

Page 4: ...rea 6 Branch delay slot of JAL X instruction in MIPS16 mode 7 Disconnect at the end of PCI burst cycle 8 Ethernet receive short packet 9 Ethernet excessive data transfer into memory 10 Ethernet transmit short packet 11 Usage PCI and Ether CEU BCU CSI using DMA mode simultaneously 12 Bus arbitration of Internal Bus Arbiter 13 XX Bit of CP0 status register 14 PCI DMA function Not applicable applicab...

Page 5: ...usted based on the content of the Length Type field RXCFC0 1 0x0f00 1554 1854 RXPFC0 1 0x0f00 1558 1858 RXUOC0 1 0x0f00 155c 185c 3 Flow control must be stopped by setting the RXCF bit in the MACC10 1 registers 0x0f00 1400 1700 to 0y0 No 3 Register content in Ether0 1 blocks Direction of usage Details When burst cycles occur on the internal bus the content of registers in the Ether0 1 blocks can b...

Page 6: ...ll registers except SCU registers 0x0f001000 0x0f001009 SDRAMU registers 0x0f000400 0x0f000409 PCIU registers 0x0f000c00 0x0f000d43 ETHER registers 0x0f001400 0x0f00193f CEU registers 0x0f000e00 0x0f000e7f No 6 Branch delay slot of JAL X instruction in MIPS16 mode Specification change notice Details A load of PC relative instruction must not be placed in the delay slot of a JAL X instruction in MI...

Page 7: ...nerated PCLK AD FRAME IRDY TRDY STOP mis understanding as disconnect D1 D0 A 0 unnecessary cycle D3 A 12 D3 D2 A 8 No 8 Ethernet receive short packet Documentation errata Details The packet size of VLAN is designed for minimum 68 bytes length but this is not described in user s manual If a VLAN packet is received with a length of 64 67 byte less than 68 byte VR4133 will be judged it as a short pac...

Page 8: ... as a jumbo frame and a transmit abort may occur though the length of actual transmitted packet is shorter than the setting of LMAX0 1 0x0f001414 0x0f001714 register 1 The length of transmitted packet indicated by SIZE 15 0 is longer than the setting of DTBS bit of XMT_CFGR0 1 0x0f001600 0x0f001900 register and the packet length is less than 32 bytes or the burst size set by the DTBS bit is 8 word...

Page 9: ... Ethernet controller the internal bus arbiter may ignore bus arbitration setting of SCUARBITSELREG and gives bus priority to Ethernet controller continuously To prevent this situation use following setting DRBS0 of RCV_CFGR0 1 0x0f001618 0x0f001918 1 and DRBS1 of RCV_CFGR0 1 0x0f001618 0x0f001918 0 This setting selects a 2 words burst size In this case the internal bus arbiter can arbitrate to oth...

Page 10: ...ns for VR4133 TM C Valid Specification Item Date published Document No Document Title 1 April 2004 U16551EJ2V0DS00 VR4133 Preliminary Data Sheet 2 February 2004 U16620EJ3V0UM00 VR4133 User Manual 10 Customer Notification ...

Page 11: ...ation 11 D Revision History Item Date published Document No Comment 1 October 2003 TPS HE B 6009 1 1st release 2 January 2004 TPS HE B 6009 2 Added item 8 to 12 3 May 2004 TPS HE B 6009 3 Modified item 10 4 June 2004 TPS HE B 6009 4 Added item 13 and 14 ...

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