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103

CHAPTER 7 WATCHDOG TIMER

7.1 Watchdog Timer Functions

The watchdog timer has the following functions.

• Watchdog timer

• Interval timer

Caution

Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register

(WDTM) (The watchdog timer and interval timer cannot be used at the same time).

(1) Watchdog timer mode

An inadvertent program loop is detected. Upon detection of the inadvertent program loop, a non-maskable

interrupt request or RESET can be generated.

Table 7-1. Watchdog Timer Overrun Detection Times

Runaway Detection Time

MCS = 1

MCS = 0

1/f

(410

1/f

(819

1/f

(819

1/f

(1.64 ms)

1/f

(1.64 ms)

1/f

(3.28 ms)

1/f

(3.28 ms)

1/f

(6.55 ms)

1/f

(6.55 ms)

1/f

(13.1 ms)

1/f

(13.1 ms)

1/f

(26.2 ms)

1/f

(26.2 ms)

1/f

(52.4 ms)

1/f

(104.9 ms)

1/f

(209.7 ms)

Remarks 1. f

: Main system clock frequency (f

or f

/2)

2. f

: Main system clock oscillation frequency

3. MCS : Oscillation mode selection register (OSMS) bit 0

4. Values in parentheses when operated at f

= 5.0 MHz.

Summary of Contents for NEC PD78081

Page 1: ... A µPD78082 µPD78082 A µPD78P083 µPD78P083 A µPD78P081 A2 µPD78083 SUBSERIES 8 BIT SINGLE CHIP MICROCONTROLLER Document No U12176EJ2V0UM00 2nd edition O D No IEU 886 Date Published May 1997 N Printed in Japan 1992 1994 ...

Page 2: ... CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD ...

Page 3: ...of Open Software Foundation Inc TRON is an abbreviation of The Realtime Operating system Nucleus ITRON is an abbreviation of Industrial TRON The export of these products from Japan is regulated by the Japanese government The export of some or all of these products may be prohibited without governmental license To export or re export some or all of these products from a country other than Japan may...

Page 4: ...re containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the qual...

Page 5: ...2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Regional Information Some information contained in this document may vary from country to country Before...

Page 6: ...erter Mode Register in Figure10 1 A D Converter Block Diagram p 122 193 10 3 1 A D converter mode register ADM 13 1 1 Standby function and Cautions have been added p 137 Figure 11 1 Serial Interface Channel 2 Block Diagram has been corrected p 146 155 11 3 4 a 11 4 2 1 d i Generation of baud rate transmit receive clock by means of main system clock have been added 76800 bps has been added to baud ...

Page 7: ...This Manual Before reading this manual you should have general knowledge of electric and logic circuits and microcontrollers For those who will be using this as a manual for the µPD78081 A 78082 A 78P083 A and 78081 A2 The µPD78081 78082 78P083 are explained as being representative de vices In case this is used as a manual for the µPD78081 A 78082 A 78P083 A or 78081 A2 please reread the product n...

Page 8: ...t Caution Information requiring particular attention Remarks Additional explanatory material Numeral representations Binary or B Decimal Hexadecimal H Examples of use in this manual are prepared for Standard quality level devices for general electronic equipment In the case of examples of use in this manual for devices which meet Special quality level requirements please use each device only after...

Page 9: ...15E µPD78P083 Data Sheet U11006J U11006E µPD78081 A 78082 A 78081 A2 Data Sheet In preparation To be prepared µPD78P083 A Data Sheet U12175J U12175E µPD78083 Subseries Special Function Register Table IEM 5599 78K 0 Series User s Manual Instruction IEU 849 IEU 1372 78K 0 Series Instruction Table U10903J 78K 0 Series Instruction Set U10904J 78K 0 Series Application Note Basics III IEA 767 U10182E Ca...

Page 10: ...MS DOS Base EEU 704 EEU 1291 PG 1500 Controller IBM PC Series PC DOS Base EEU 5008 U10540E IE 78000 R EEU 810 U11376E IE 78000 R A U10057J U10057E IE 78000 R BK EEU 867 EEU 1427 IE 78078 R EM U10775J U10775E EP 78083 EEU 5003 EEU 1529 SM78K0 System Simulator Windows Base Reference U10181J U10181E SM78K Series System Simulator External component user U10092J U10092E open interface specifications ID...

Page 11: ...zy Inference Development Support System Fuzzy Inference Debugger EEU 921 EEU 1458 Other Documents Document name Document No Japanese English IC PACKAGE MANUAL C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grade on NEC Semiconductor Devices C11531J C11531E Reliability Quality Control on NEC Semiconductor Devices C10983J C10983E Electric Static Discharge ESD Test ME...

Page 12: ...P03 Port 0 17 2 2 2 P10 to P17 Port 1 17 2 2 3 P30 to P37 Port 3 18 2 2 4 P50 to P57 Port 5 18 2 2 5 P70 to P72 Port 7 19 2 2 6 P100 to P101 Port 10 19 2 2 7 AVREF 20 2 2 8 AVDD 20 2 2 9 AVSS 20 2 2 10 RESET 20 2 2 11 X1 and X2 20 2 2 12 VDD 20 2 2 13 VSS 20 2 2 14 VPP µPD78P083 only 20 2 2 15 IC Mask ROM version only 21 2 2 16 NC 44 pin plastic QFP versions only 21 2 3 Pin Input Output Circuits a...

Page 13: ...Port 3 58 4 2 4 Port 5 59 4 2 5 Port 7 60 4 2 6 Port 10 62 4 3 Port Function Control Registers 63 4 4 Port Function Operations 67 4 4 1 Writing to input output port 67 4 4 2 Reading from input output port 67 4 4 3 Operations on input output port 67 CHAPTER 5 CLOCK GENERATOR 69 5 1 Clock Generator Functions 69 5 2 Clock Generator Configuration 69 5 3 Clock Generator Control Register 71 5 4 System C...

Page 14: ...nctions 115 9 2 Buzzer Output Control Circuit Configuration 115 9 3 Buzzer Output Function Control Registers 116 CHAPTER 10 A D CONVERTER 119 10 1 A D Converter Functions 119 10 2 A D Converter Configuration 119 10 3 A D Converter Control Registers 122 10 4 A D Converter Operations 126 10 4 1 Basic operations of A D converter 126 10 4 2 Input voltage and conversion results 128 10 4 3 A D converter...

Page 15: ... Register 206 15 2 PROM Programming 207 15 2 1 Operating modes 207 15 2 2 PROM write procedure 209 15 2 3 PROM reading procedure 213 15 3 Erasure Procedure µPD78P083DU Only 214 15 4 Opaque Film Masking the Window µPD78P083DU Only 214 15 5 Screening of One Time PROM Versions 214 CHAPTER 16 INSTRUCTION SET 215 16 1 Legends Used in Operation List 216 16 1 1 Operand identifiers and description methods...

Page 16: ...ircuit Emulators to 78K 0 Series In Circuit Emulator 240 APPENDIX B EMBEDDED SOFTWARE 243 B 1 Real time OS 244 B 2 Fuzzy Inference Development Support System 245 APPENDIX C REGISTER INDEX 247 C 1 Register Index 247 APPENDIX D REVISION HISTORY 249 ...

Page 17: ...gram 61 4 9 P100 to P101 Block Diagram 62 4 10 Port Mode Register Format 65 4 11 Pull Up Resistor Option Register Format 66 5 1 Block Diagram of Clock Generator 70 5 2 Processor Clock Control Register Format 71 5 3 Oscillation Mode Selection Register Format 72 5 4 Main System Clock Waveform due to Writing to OSMS 5 5 External Circuit of Main System Clock Oscillator 73 5 6 Examples of Oscillator wi...

Page 18: ...e 111 8 2 Clock Output Control Circuit Block Diagram 112 8 3 Timer Clock Select Register 0 Format 113 8 4 Port Mode Register 3 Format 114 9 1 Buzzer Output Control Circuit Block Diagram 115 9 2 Timer Clock Select Register 2 Format 117 9 3 Port Mode Register 3 Format 118 10 1 A D Converter Block Diagram 120 10 2 A D Converter Mode Register Format 123 10 3 A D Converter Input Select Register Format ...

Page 19: ... Word Configuration 180 12 8 Flowchart from Non Maskable Interrupt Request Generation to Acknowledgment 182 12 9 Non Maskable Interrupt Request Acknowledge Timing 182 12 10 Non Maskable Interrupt Request Acknowledge Operation 183 12 11 Interrupt Request Acknowledge Processing Algorithm 185 12 12 Interrupt Request Acknowledge Timing Minimum Time 186 12 13 Interrupt Request Acknowledge Timing Maximu...

Page 20: ... ix FIGURE 4 4 Fig No Title Page 15 6 PROM Read Timing 213 A 1 Development Tool Configuration 232 A 2 EV 9200G 44 Drawing For Reference Only 241 A 3 EV 9200G 44 Footprint For Reference Only 242 ...

Page 21: ...rs 5 and 6 Configurations 82 6 5 8 Bit Timer Event Counters 5 and 6 Interval Times 92 6 6 8 Bit Timer Event Counters 5 and 6 Square Wave Output Ranges 95 7 1 Watchdog Timer Overrun Detection Times 103 7 2 Interval Times 104 7 3 Watchdog Timer Configuration 105 7 4 Watchdog Timer Overrun Detection Time 109 7 5 Interval Timer Interval Time 110 8 1 Clock Output Control Circuit Configuration 112 9 1 B...

Page 22: ...ter HALT Mode Release 197 13 3 STOP Mode Operating Status 198 13 4 Operation after STOP Mode Release 200 14 1 Hardware Status after Reset 1 2 203 14 1 Hardware Status after Reset 2 2 204 15 1 Differences between the µPD78P083 and Mask ROM Versions 205 15 2 Examples of Memory Size Switching Register Settings 206 15 3 PROM Programming Operating Modes 207 16 1 Operand Identifiers and Description Meth...

Page 23: ... xii MEMO ...

Page 24: ...ration Instruction set suited to system control Bit manipulation possible in all address spaces Multiply and divide instructions 33 I O ports 8 bit resolution A D converter 8 channels Serial interface 1 channel 3 wire serial I O UART mode 1 channel Timer 3 channels 8 bit timer event counter 2 channels Watchdog timer 1 channel Vectored Interrupt Source 13 Supply voltage VDD 1 8 to 5 5 V Program Mem...

Page 25: ...ROM µPD78082GB 3B4 44 pin plastic QFP 10 10 mm Mask ROM µPD78082GB 3BS MTX 44 pin plastic QFP 10 10 mm Mask ROM µPD78P083CU 42 pin plastic shrink DIP 600 mil One Time PROM µPD78P083DU 42 pin ceramic shrink DIP with window 600 mil EPROM µPD78P083GB 3B4 44 pin plastic QFP 10 10 mm One Time PROM µPD78P083GB 3BS MTX 44 pin plastic QFP 10 10 mm One Time PROM µPD78081GB A 3B4 44 pin plastic QFP 10 10 mm...

Page 26: ...Not applicable µPD78P083GB 3B4 44 pin plastic QFP 10 10 mm Standard µPD78P083GB 3BS MTX 44 pin plastic QFP 10 10 mm Standard µPD78081GB A 3B4 44 pin plastic QFP 10 10 mm Special µPD78082GB A 3B4 44 pin plastic QFP 10 10 mm Special µPD78P083CU A 42 pin plastic shrink DIP 600 mil Special µPD78P083GB A 3B4 44 pin plastic QFP 10 10 mm Special µPD78P083GB A 3BS MTXNote 44 pin plastic QFP 10 10 mm Speci...

Page 27: ...01 TI6 TO6 P70 RXD SI2 P71 TXD SO2 P72 ASCK SCK2 P17 ANI7 P16 ANI6 P15 ANI5 P14 ANI4 P13 ANI3 P12 ANI2 P11 ANI1 P10 ANI0 AVSS AVREF 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P55 P56 P57 P30 P31 P32 P33 P34 P35 PCL P36 BUZ P37 P00 P01 INTP1 P02 INTP2 P03 INTP3 RESET IC VPP X2 X1 VDD AVDD Cautions 1 Be sure to connect IC Internally Connected pin to VSS directly 2 Connect AVDD pi...

Page 28: ... AVSS pin to VSS 4 Connect NC pin to VSS for noise protection It can be left open Remark Pin connection in parenthesis is intended for the µPD78P083 1 2 3 4 5 6 7 8 9 10 11 P03 INTP3 P02 INTP2 P01 INTP1 P00 P37 P36 BUZ P35 PCL P34 P33 P32 NC 33 32 31 30 29 28 27 26 25 24 23 P12 ANI2 P13 ANI3 P14 ANI4 P15 ANI5 P16 ANI6 P17 ANI7 P72 ASCK SCK2 P71 TxD SO2 P70 RxD SI2 P101 TI6 TO6 P100 TI5 TO6 P11 ANI...

Page 29: ... Data AVSS Analog Ground SCK2 Serial Clock BUZ Buzzer Clock SI2 Serial Input IC Internally Connected SO2 Serial Output INTP1 to INTP3 Interrupt from Peripherals TI5 TI6 Timer Input NC Non connection TO5 to TO6 Timer Output P00 to P03 Port 0 TxD Transmit Data P10 to P17 Port 1 VDD Power Supply P30 to P37 Port 3 VPP Programming Power Supply P50 to P57 Port 5 VSS Ground P70 to P72 Port 7 X1 X2 Crysta...

Page 30: ...vidually connect to VSS via a pull down resistor 2 VSS Connect to the ground 3 RESET Set to the low level 4 Open Do not connect anything 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 VSS A4 A3 A2 A1 A0 A10 A11 A12 A13 A14 D7 D6 D5 D4 D3 D2 D1 D0 VSS VSS 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 A5 A6 A7 OE CE PGM A8 A9 RESET VPP Open L VDD VDD L L ...

Page 31: ...r Supply D0 to D7 Data Bus VPP Programming Power Supply OE Output Enable VSS Ground PGM Program 44 pin plastic QFP 10 10 mm µPD78P083GB 3B4 78P083GB 3BS MTX µPD78P083GB A 3B4 78P083GB A 3BS MTXNote 1 2 3 4 5 6 7 8 9 10 11 A9 A8 PGM L 33 32 31 30 29 28 27 26 25 24 23 D2 D3 D4 D5 D6 D7 A14 A13 A12 A11 A10 D1 D0 V SS V SS V DD V DD L Open V PP RESET L A0 A1 A2 A3 A4 V SS A5 A6 A7 OE CE 12 13 14 15 16...

Page 32: ...added to the µPD78002 Basic subseries for control applications On chip UART and operable at low voltage 1 8 V I O and FIP C D of the µPD78044F are enhanced Total display outputs 53 pins I O and FIP C D of the µPD78044H are enhanced Total display outputs 48 pins N ch open drain I O is added to the µPD78044F Total display outputs 34 pins Basic subseries for FIP driving Total display outputs 34 pins ...

Page 33: ...8 ch division 3 wire 1 ch µPD78014H 2 ch 53 µPD78018F 8K to 60K µPD78014 8K to 32K 2 7 V µPD780001 8K 1 ch 39 µPD78002 8K to 16K 1 ch 53 Available µPD78083 8 ch 1 ch UART 1 ch 33 1 8 V Inverter µPD780964 8K to 32K 3 ch Note 1 ch 8 ch 2 ch UART 2 ch 47 2 7 V Available control µPD780924 8 ch FIP driving µPD780208 32K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2 7 V µPD780228 48K to 60K 3 ch 1 ch 72 4 5...

Page 34: ...70 SO2 TXD P71 SCK2 ASCK P72 ANI0 P10 ANI7 P17 AVDD AVSS AVREF INTP1 P01 INTP3 P03 BUZ P36 PCL P35 PORT 0 PORT 1 PORT 3 PORT 5 PORT 7 PORT 10 SYSTEM CONTROL 8 bit TIMER EVENT COUNTER 5 BUZZER OUTPUT INTERRUPT CONTROL A D CONVERTER SERIAL INTERFACE 2 WATCHDOG TIMER CLOCK OUTPUT CONTROL 8 bit TIMER EVENT COUNTER 6 78K 0 CPU CORE ROM RAM P00 P01 P03 P10 P17 P30 P37 P50 P57 P70 P72 P100 P101 RESET X1 ...

Page 35: ...erter 8 bit resolution 8 channels Serial interface 3 wire serial I O UART mode selectable 1 channel Timer 8 bit timer event counter 2 channels Watchdog timer 1 channel Timer output 2 pins 8 bit PWM output enable Clock output 19 5 kHz 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz 2 5 MHz and 5 0 MHz 5 0 MHz operation with main system clock Buzzer output 1 2 kHz 2 4 kHz 4 9 kHz and 9 8 kHz 5 0 ...

Page 36: ...1 78082 and 78P083 the µPD78081 A 78082 A and 78P083 A and the µPD78081 A2 Part Number µPD78081 µPD78081 A µPD78081 A2 µPD78082 µPD78082 A Item µPD78P083 µPD78P083 A Quality grade Standard Special Supply voltage VDD 1 8 to 5 5 V VDD 4 5 to 5 5 V Operating ambient temperature TA 40 to 85 C TA 40 to 125 C Electrical specifications Please refer to the individual data sheets ...

Page 37: ...14 CHAPTER 1 OUTLINE MEMO ...

Page 38: ...port it is possible to connect a pull up resistor by software Note P30 P34 Input output Port 3 Input P35 8 bit input output port PCL P36 Input output is specifiable bit wise BUZ P37 When used as the input port it is possible to connect a pull up resistor by software P50 P57 Input output Port 5 Input 8 bit input output port A maximum of 7 out of 8 ports can drive LEDs directly Input output is speci...

Page 39: ...I0 ANI7 Input A D converter analog input Input P10 P17 AVREF Input A D converter reference voltage input AVDD A D converter analog power supply Connected to VDD AVSS A D converter ground potential Connected to VSS RESET Input System reset input X1 Input Main system clock oscillation crystal connection X2 VDD Positive power supply VPP High voltage applied during program write verification Connected...

Page 40: ...3 function as external interrupt request input pins which are capable of specifying the valid edges rising edge falling edge and both rising and falling edges 2 2 2 P10 to P17 Port 1 These are 8 bit input output ports Besides serving as input output ports they function as an A D converter analog input The following operating modes can be specified bit wise 1 Port mode These ports function as 8 bit...

Page 41: ...M3 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode These ports function as clock output and buzzer output a PCL Clock output pin b BUZ Buzzer output pin 2 2 4 P50 to P57 Port 5 These are 8 bit input output ports They can be specified bit wise as input output ports with port mode register 5 PM5 When they ...

Page 42: ...terface serial data input output pins d ASCK Asynchronous serial interface serial clock input pin Caution When this port is used as a serial interface the I O and output latches must be set according to the function the user requires For the setting see the operation mode setting list in Table 11 2 Serial Interface Channel 2 Operating Mode Settings 2 2 6 P100 to P101 Port 10 These are 2 bit input ...

Page 43: ...r Always use the same voltage as that of the VSS pin even when A D converter is not used 2 2 10 RESET This is a low level active system reset input pin 2 2 11 X1 and X2 Crystal resonator connect pins for main system clock oscillation For external clock supply input it to X1 and its inverted signal to X2 2 2 12 VDD Positive power supply pin 2 2 13 VSS Ground potential pin 2 2 14 VPP µPD78P083 only ...

Page 44: ...ible wire in the normal operating mode When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins is too long or an external noise is input to the IC pin the user s program may not run normally Connect IC pins to VSS pins directly VSS IC As short as possible 2 2 16 NC 44 pin plastic QFP versions only Not internally connected Please connect to Vss...

Page 45: ...A P71 SO2 TxD 5 A P72 SCK2 ASCK 8 A P100 TI5 TO5 8 A P101 TI6 TO6 RESET 2 Input AVREF Connect to VSS AVDD Connect to VDD AVSS Connect to VSS VPP µPD78P083 Connect directly to VSS NC 44 pin plastic QFP Connect to VSS can also leave open version IC Mask ROM version Connect directly to VSS 2 3 Pin Input Output Circuits and Recommended Connection of Unused Pins Types of input output circuits of the pi...

Page 46: ...able output disable data VDD P ch N ch Type 2 Type 5 A Schmitt Triggered Input with Hysteresis Characteristics Type 11 Type 8 A pull up enable VDD P ch IN OUT output disable data VDD P ch N ch pull up enable VDD P ch IN OUT output disable data VDD P ch N ch P ch comparator N ch input enable VREF Threshold voltage ...

Page 47: ...24 CHAPTER 2 PIN FUNCTION MEMO ...

Page 48: ...e General Registers 32 8 bits Internal ROM 8192 8 bits CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Unusable Program memory space Internal High speed RAM 256 8 bits Special Function Registers SFRs 256 8 bits FF00H FEFFH FEE0H FEDFH FE00H FDFFH 2000H 1FFFH 0000H 1FFFH 0000H 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH FFFFH ...

Page 49: ...M 16384 8 bits CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Unusable Program memory space Internal High speed RAM 384 8 bits Special Function Registers SFRs 256 8 bits FF00H FEFFH FEE0H FEDFH FD80H FD7FH 4000H 3FFFH FFFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 3FFFH 0000H 0000H ...

Page 50: ...OM 24576 8 bits CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Unusable Program memory space Internal High speed RAM 512 8 bits Special Function Registers SFRs 256 8 bits FF00H FEFFH FEE0H FEDFH FD00H FCFFH 6000H 5FFFH FFFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 5FFFH 0000H 0000H ...

Page 51: ...The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area Of the 16 bit address low order 8 bits are stored at even addresses and high order 8 bits are stored at odd addresses Table 3 1 Vector Table Vector Table Address Interrupt Request 0000H RESET input 0004H INTWDT 0008H INTP1 000AH INTP2 000CH INTP3 0018H INTSER 001AH I...

Page 52: ...the instruction to be executed next or the address of a register or memory to be manipulated when an instruction is executed is called addressing The address of the instruction to be executed next is addressed by the program counter PC for details refer to 3 3 Instruction Address Addressing To address the memory that is manipulated when an instruction is executed the µPD78083 Subseries is provided...

Page 53: ...bits Unusable Internal High speed RAM 256 8 bits Special Function Registers SFRs 256 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH FE20H FE1FH FE00H FDFFH 2000H 1FFFH FFFFH 0000H ...

Page 54: ...bits Unusable Internal High speed RAM 384 8 bits Special Function Registers SFRs 256 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH FE20H FE1FH FD80H FD7FH 4000H 3FFFH FFFFH 0000H ...

Page 55: ... bits Unusable Internal High speed RAM 512 8 bits Special Function Registers SFRs 256 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH FE20H FE1FH FD00H FCFFH 6000H 5FFFH FFFFH 0000H ...

Page 56: ...tically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 7 Program Counter Configuration 2 Program status word PSW The program status word is an 8 bit register consisting of variou...

Page 57: ... of the four register banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruction execution is stored d Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases e In service priority flag ISP This flag manages the priority of acknowledgeable maskable vectored inte...

Page 58: ... pointer SP This is a 16 bit register to hold the start address of the memory stack area Only the internal high speed RAM area FE00H FEFFH for the µPD78081 FD80H FEFFH for the µPD78082 and FD00H FEFFH for the µPD78P083 can be set as the stack area Figure 3 9 Stack Pointer Configuration The SP is decremented ahead of write save to the stack memory and is incremented after read reset from the stack ...

Page 59: ...ht 8 bit registers X A C B E D L and H Each register can also be used as an 8 bit register Two 8 bit registers can be used in pairs as a 16 bit register AX BC DE and HL They can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Register banks to be used for instruction execution are set with the CPU control instruction SEL RBn Becaus...

Page 60: ...anipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address Table 3 2 gives a list of special function registers The meaning of items in the table is as follows Symbol Symbols indicating the addresses of special function register These symbo...

Page 61: ...M6 R FF56H Timer clock select register 6 TCL6 R W FF57H 8 bit timer mode control register 6 TMC6 FF70H Asynchronous serial interface mode register ASIM FF71H Asynchronous serial interface status register ASIS R FF72H Serial operating mode register 2 CSIM2 R W FF73H Baud rate generator control register BRGC FF74H Transmit shift register TXS SIO2 W FFH Receive buffer register RXB R FF80H A D convert...

Page 62: ...gister IMS Note FFF2H Oscillation mode selection register OSMS W 00H FFF3H Pull up resistor option register H PUOH R W FFF7H Pull up resistor option register L PUOL FFF9H Watchdog timer mode register WDTM FFFAH Oscillation stabilization time select register OSTS 04H FFFBH Processor clock control register PCC Table 3 2 Special Function Register List 2 2 Manipulatable Bit Unit 8 bits 1 bit 16 bits N...

Page 63: ... information is set to the PC and branched by the following addressing For details of instructions refer to 78K 0 USER S MANUAL Instruction IEU 1372 3 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacem...

Page 64: ...ddr16 or CALLF addr11 instruction is executed The CALL addr16 and BR addr16 instruction can branch in the entire memory space The CALLF addr11 instruction branches to an area of addresses 0800H through 0FFFH Illustration In the case of CALL addr16 and BR addr16 instructions 15 0 PC 8 7 7 0 fa10 8 11 10 0 0 0 0 1 6 4 3 CALLF fa7 0 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr In the case of CALLF a...

Page 65: ...o the program counter PC and branched Before the CALLT addr5 instruction is executed table indirect addressing is performed This instruction references an address stored in the memory table at addresses 40H through 7FH and can branch in the entire memory space Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective Address 1 Effective Address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 1 1...

Page 66: ...5 0 PC 8 7 3 3 4 Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Illustration ...

Page 67: ...to be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values which become decimal correction targets ROR4 ROL4 A register for storage of digit data which undergoes digit rotation Operand format Because implied addressing can be automatically employe...

Page 68: ... operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with function names X A C B E D L H AX BC DE and HL as well as absolute names R0 to R7 and RP0 to RP3 Description example MOV A C when selecting C register as r Oper...

Page 69: ... by the immediate data in an instruction word Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH Illustration Memory 0 7 OP code saddr16 low saddr16 high ...

Page 70: ...a FF00H through FF1FH to which short direct addressing is applied is a part of the entire SFR area To this area ports frequently accessed by the program and the compare registers and capture registers of timer event counters are mapped These SFRs can be manipulated with a short byte length and a few clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it...

Page 71: ...dr offset α Description example MOV 0FE30H 50H when setting saddr to FE30H and immediate data to 50H Operation code 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0 30H saddr offset 0 1 0 1 0 0 0 0 50H immediate data Illustration When 8 bit immediate data is 20H to FFH α 0 When 8 bit immediate data is 00H to 1FH α 1 ...

Page 72: ...rd This addressing is applied to the 240 byte spaces FF00H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PM0 A when selecting PM0 FF20H as sfr Operation code 1 ...

Page 73: ...gister bank select flags RBS0 and RBS1 and register pair specify code in an instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE when selecting DE as register pair Operation code 1 0 0 0 0 1 0 1 Illustration 16 0 8 D 7 E 0 7 7 0 A DE Memory Contents of addressed memory are transferred Memory address s...

Page 74: ...e HL register pair to be accessed is in the register bank specified by the register bank select flags RBS0 and RBS1 Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL byte Description example MOV A HL 10H when setting byte to 10H...

Page 75: ...er to 16 bits as a positive number A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL B HL C Description example In the case of MOV A HL B Operation code 1 0 1 0 1 0 1 1 3 4 9 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatica...

Page 76: ...orts Figure 4 1 shows the port configuration Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also serve as on chip hardware input output pins Figure 4 1 Port Types Port 0 Port 7 Port 1 P00 P70 P72 P10 P03 P17 Port 10 Port 3 P100 P101 P30 P37 Port 5 P50 P57 ...

Page 77: ...ecifiable bit wise BUZ P37 When used as the input port it is possible to connect a pull up resistor by software P50 P57 Input output Port 5 8 bit input output port A maximum of 7 out of 8 ports can drive LEDs directly Input output is specifiable bit wise When used as the input port it is possible to connect a pull up resistor by software P70 Input output Port 7 SI2 RxD P71 3 bit input output port ...

Page 78: ...de output mode in 1 bit units with the port mode register 0 PM0 P00 pin is input only port When P01 to P03 pins are used as input ports an on chip pull up resistor can be used to them in 3 bit units with a pull up resistor option register L PUOL Dual functions include external interrupt request input RESET input sets port 0 to input mode Figures 4 2 and 4 3 show block diagrams of port0 Caution Bec...

Page 79: ... 4 3 P01 to P03 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal P00 RD Internal bus P ch WRPM WRPORT RD WRPUO VDD P01 INTP1 P03 INTP3 Selector PUO0 Output Latch P01 to P03 PM01 PM03 Internal bus ...

Page 80: ...l up resistor option register L PUOL Dual functions include an A D converter analog input RESET input sets port 1 to input mode Figure 4 4 shows a block diagram of port 1 Caution A pull up resistor cannot be used for pins used as A D converter analog input Figure 4 4 P10 to P17 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 1 read signal WR Port 1 write signal P c...

Page 81: ...d to them in 8 bit units with a pull up resistor option register L PUOL Dual functions include clock output and buzzer output RESET input sets port 3 to input mode Figure 4 5 shows a block diagram of port 3 Figure 4 5 P30 to P37 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 3 read signal WR Port 3 write signal P ch WRPM WRPORT RD WRPUO VDD Selector PUO3 Output La...

Page 82: ... resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL A maximum of 7 out of 8 ports can drive LEDs directly RESET input sets port 5 to input mode Figure 4 6 shows a block diagram of port 5 Figure 4 6 P50 to P57 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 5 read signal WR Port 5 write signal P ch WRPM WRPORT RD WRPUO VDD Sel...

Page 83: ...interface channel 2 data input output and clock input output RESET input sets the input mode Port 7 block diagrams are shown in Figures 4 7 and 4 8 Caution When used as a serial interface set the input output and output latch according to its functions For the setting method refer to Table 11 2 Serial Interface Channel 2 Operating Mode Settings Figure 4 7 P70 Block Diagram PUO Pull up resistor opt...

Page 84: ...lock Diagram PUO Pull up resistor option register PM Port mode register RD Port 7 read signal WR Port 7 write signal P ch WRPM WRPORT RD WRPUO VDD Selector PUO7 Output Latch P71 and P72 PM71 PM72 Internal bus Alternate Function P71 SO2 TxD P72 SCK2 ASCK ...

Page 85: ...it by means of pull up resistor option register H PUOH These pins are dual function pins and serve as timer inputs outputs RESET input sets the input mode The port 10 block diagram is shown in Figure 4 9 Figure 4 9 P100 to P101 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 10 read signal WR Port 10 write signal P ch WRPM WRPORT RD WRPUO VDD Selector PUO10 Output ...

Page 86: ...M10 are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets registers to FFH When port pins are used as the dual function pins set the port mode register and output latch according to Table 4 3 Cautions 1 P00 pin is input only pin 2 As port 0 has a dual function as external interrupt request input when the port function output mode is specified and the output l...

Page 87: ...put 1 TO6 Output 0 0 Dual functions Name P PM Input Output Pin Name Note If a read instruction is performed to these pins when they are used as an alternate function read data is to be undefined Caution When port 7 is used for serial interface the I O latch or output latch must be set according to its function For the setting methods see Table 11 2 Serial Interface Channel 2 Operating Mode Setting...

Page 88: ...16 PM15 PM14 PM13 PM12 PM11 PM10 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM7 FF27H FFH R W 1 1 1 1 1 PM72 PM71 PM70 1 1 PM10 PMmn Pmn Pin Input Output Mode Selection m 0 1 3 5 7 10 n 0 to 7 0 1 Output mode output buffer ON Input mode output buffer OFF FF2AH FFH R W 1 1 1 1 1 1 PM101 PM100 Caution Set 1 to the bits 0 4 to 7 of PM0 bits 3 to 7 of PM7 and bits ...

Page 89: ...OL are set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Cautions 1 P00 pin does not incorporate a pull up resistor 2 When port 1 is used as dual function pin an on chip pull up resistor cannot be used even if 1 is set in PUOL bit 1 PUO1 Figure 4 11 Pull Up Resistor Option Register Format Caution Set 0 to the bits 0 1 3 to 7 of PUOH and bits 2 4 6 of P...

Page 90: ...latch contents for pins specified as input are undefined except for the manipulated bit 4 4 2 Reading from input output port 1 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin status is read by a transfer instruction The output latch contents do not change 4 4 3 Operations on input output port 1 Output mode An ope...

Page 91: ...68 CHAPTER 4 PORT FUNCTIONS MEMO ...

Page 92: ...ble Main system clock oscillator This circuit oscillates at frequencies of 1 to 5 0 MHz Oscillation can be stopped by executing the STOP instruction 5 2 Clock Generator Configuration The clock generator consists of the following hardware Table 5 1 Clock Generator Configuration Item Configuration Control register Processor clock control register PCC Oscillation mode selection register OSMS Oscillat...

Page 93: ... Clock Oscillator X2 X1 STOP PCC2 PCC1 Internal Bus Standby Control Circuit 2 fXX 2 2 fXX 2 3 fXX 2 4 fXX Prescaler Clock to Peripheral Hardware Prescaler Oscillation Mode Selection Register fXX CPU Clock fCPU Scaler Selector fX 2 fX MCS Processor Clock Control Register PCC0 3 Selector ...

Page 94: ...Caution Set 0 to the bits 3 to 7 Remarks 1 fXX Main system clock frequency fX or fX 2 2 fX Main system clock oscillator frequency 3 MCS Bit 0 of oscillation mode selection register OSMS 4 Figures in parentheses indicate minimum instruction execution time 2fCPU when operating at fX 5 0 MHz 0 0 0 0 PCC2 PCC1 PCC0 PCC FFFBH 04H R W 7 6 5 4 Symbol Address After Reset R W 0 7 6 3 2 0 1 0 0 fXX 2 PCC2 C...

Page 95: ...ormat Cautions 1 Writing to OSMS should be performed only immediately after reset signal release and before peripheral hardware operation starts As shown in Figure 5 4 below writing data including same data as previous to OSMS cause delay of main system clock cycle up to 2 fx during the write operation Therefore if this register is written during the operation in peripheral hardware which operates...

Page 96: ... clock Cautions 1 Do not execute the STOP instruction if an external clock is used This is because the X2 pin is connected to VDD via a pull up register 2 When using a main system clock oscillator carry out wiring in the broken line area in Figure 5 5 to prevent any effects from wiring capacities Minimize the wiring length Do not allow wiring to intersect with other signal conductors Do not allow ...

Page 97: ...uits b Signal conductors intersect is too long with each other c Changing high current is too near a d Current flows through the grounding line signal conductor of the ocsillator potential at points A B and C fluctuate IC X2 X1 X2 X1 PORTn n 0 1 3 5 7 10 IC IC X2 X1 High Current IC X2 A B C Pnm VDD High Current X1 ...

Page 98: ... 5 CLOCK GENERATOR Figure 5 6 Examples of Oscillator with Bad Connection 2 2 c Signals are fetched 5 4 2 Scaler The scaler divides the main system clock oscillator output fXX and generates various clocks IC X2 X1 ...

Page 99: ...on register OSMS a Upon generation of RESET signal the lowest speed mode of the main system clock 12 8 µs when operated at 5 0 MHz is selected PCC 04H OSMS 00H Main system clock oscillation stops while low level is applied to RESET pin b The six types of CPU clocks 0 4 µs 0 8 µs 1 6 µs 3 2 µs 6 4µs 12 8 µs 5 0 MHz can be selected by setting the PCC and OSMS c Two standby modes the STOP and HALT mo...

Page 100: ...for CPU Clock Switchover 1 0 0 1 1 0 1 0 0 1 0 0 0 0 0 PCC0 PCC2 PCC1 0 0 0 0 1 1 0 0 0 1 1 1 8 instructions 2 instructions 4 instructions 4 instructions 2 instructions 8 instructions 4 instructions 4 instructions 2 instructions 8 instructions 8 instructions 2 instructions Set Values After Switchover Set Values before Switchover 1 instruction 1 instruction 1 instruction PCC1 PCC2 PCC0 PCC1 PCC2 PC...

Page 101: ...ation stabilization time 217 fX is secured automatically After that the CPU starts executing the instruction at the minimum speed of the main system clock 12 8 µs when operated at 5 0 MHz 2 After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speeds the processor clock control register PCC and oscillation mode selection register OSMS are rewritten and...

Page 102: ...askable interrupt requests and RESET at the preset time intervals See CHAPTER 7 WATCHDOG TIMER 3 Clock output control circuit This circuit supplies a clock obtained by dividing the main system clock to other devices See CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT 4 Buzzer output control circuit This circuit outputs the buzzer frequency obtained by dividing the main system clock See CHAPTER 9 BUZZER OUT...

Page 103: ...09 6 µs 800 ns 1 6 µs 23 1 fX 24 1 fX 211 1 fX 212 1 fX 23 1 fX 24 1 fX 1 6 µs 3 2 µs 409 6 µs 819 2 µs 1 6 µs 3 2 µs 24 1 fX 25 1 fX 212 1 fX 213 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 213 1 fX 214 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 2...

Page 104: ...409 6 µs 819 2 µs 1 6 µs 3 2 µs 24 1 fX 25 1 fX 212 1 fX 213 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 213 1 fX 214 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 1 fX 28 1 fX 215 1 fX 216 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ...

Page 105: ...it timer mode control register 5 and 6 TMC5 TMC6 Port mode register 10 PM10 Figure 6 1 8 Bit Timer Event Counters 5 and 6 Block Diagram Note Refer to Figures 6 2 for details of configurations of 8 bit timer event counters 5 and 6 output control circuits Remark n 5 6 TCEn LVSn LVRn TMC n6 TMC n1 TOEn TCL n3 TCL n2 TCL n1 TCL n0 8 Bit Compare Register CRn0 8 Bit Timer Register n TMn Internal Bus Int...

Page 106: ...0 Bit 0 of port mode register 10 PM10 PM101 Bit 1 of PM10 Remarks 1 The section in the broken line is an output control circuit 2 n 5 6 RESET LVRn LVSn TMCn1 TMCn6 OVFn INTTMn TCEn INTTMn R S Q PWM Output Circuit Timer Output F F2 Level Invert R S INV Q TMCn1 TMCn6 Selector P100 P101 Output Latch PM100 PM101Note TO5 P100 TI5 TO6 P101 TI6 TOEn ...

Page 107: ...aution When using the PWM mode please set the CRn0 value before setting TMCn n 5 6 to the PWM mode 2 8 bit timer registers 5 and 6 TM5 TM6 These are 8 bit registers to count count pulses TM5 and TM6 are read with an 8 bit memory manipulation instruction RESET input sets TM5 and TM6 to 00H 6 3 8 Bit Timer Event Counters 5 and 6 Control Registers The following three types of registers are used to co...

Page 108: ...1 0 Symbol TCL5 FF52H 00H R W Address After Reset R W TCL53 TCL52 TCL51 TCL50 0 0 0 0 TI5 falling edgeNote 0 0 0 1 TI5 rising edgeNote 0 1 1 0 0 1 1 1 fXX 2 fX 2 2 5 MHz fX 2 2 1 25 MHz 1 0 0 0 fXX 2 2 fX 2 2 1 25 MHz fX 2 3 625 kHz 0 1 0 0 0 1 0 1 2fXX Setting prohibited fX 5 0 MHz fXX fX 5 0 MHz fX 2 2 5 MHz 1 0 0 1 fXX 2 3 fX 2 3 625 kHz fX 2 4 313 kHz 1 0 1 0 fXX 2 4 fX 2 4 313 kHz fX 2 5 156 ...

Page 109: ...theses when operated at fX 5 0 MHz 0 0 0 0 TCL63 TCL62 TCL61 TCL60 7 6 5 4 3 2 1 0 Symbol TCL6 TCL63 TCL62 TCL61 TCL60 0 0 0 0 TI6 falling edge Note 0 0 0 1 TI6 rising edge Note 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 MCS 1 8 bit Timer Register 6 Count Clock Selection MCS 0 Other than above Setting prohibited FF56H 00H Address After Reset 2fX...

Page 110: ...must be stopped before setting TMC5 2 If LVS5 and LVR5 are read after data are set they will be 0 3 Set 0 to the bits 4 and 5 TCE5 TMC56 0 0 LVS5 LVR5 TMC51 TOE5 7 6 5 4 3 2 1 0 Symbol TMC5 FF53H 00H R W Address After Reset R W TOE5 8 Bit Timer Event Counter 5 Output Control 0 Output disabled Port mode 1 Output enabled TMC51 0 Active high 1 Active low In PWM Mode In Other Modes Active level select...

Page 111: ...st be stopped before setting TMC6 2 If LVS6 and LVR6 are read after data are set they will be 0 3 Set 0 to the bits 4 and 5 TCE6 TMC66 0 0 LVS6 LVR6 TMC61 TOE6 7 6 5 4 3 2 1 0 Symbol TMC6 FF57H 00H R W Address After Reset R W TOE6 8 Bit Timer Event Counter 6 Output Control 0 Output disabled Port mode 1 Output enabled TMC61 0 Active high 1 Active low In PWM Mode In Other Modes Active level selectio...

Page 112: ...101 and output latches of P100 and P101 to 0 PM10 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM10 to FFH Figure 6 7 Port Mode Register 10 Format Caution Set 1 to the bits 2 to 7 0 1 2 3 4 5 6 7 Symbol PM100 FF2AH FFH R W Address After Reset R W PM101 1 1 1 1 1 1 PM10 PM10n P10n Pin Input Output Mode Selection n 0 1 0 Output mode output buffer ON 1 Input mode outp...

Page 113: ...t timer registers 5 and 6 TM5 and TM6 match the values set to CR50 and CR60 counting continues with the TM5 and TM6 values cleared to 0 and the interrupt request signals INTTM5 and INTTM6 are generated Count clock of TM5 can be selected with the timer clock select register 5 TCL5 Count clock of TM6 can be selected with the timer clock select register 6 TCL6 Figure 6 8 8 Bit Timer Mode Control Regi...

Page 114: ... INTTMn TCEn CRn0 TOn Interval Time Interval Time Interval Time Interrupt Request Acknowledge Interrupt Request Acknowledge N N N N Clear Count start Clear t 00 01 N 00 01 N 00 01 N Figure 6 9 Interval Timer Operation Timings Remarks 1 Interval time N 1 t N 00H to FFH 2 n 5 6 ...

Page 115: ... fX 212 1 fX 213 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 213 1 fX 214 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 1 fX 28 1 fX 215 1 fX 216 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 1 fX 29 1 fX 216 1 fX ...

Page 116: ... the TM5 and TM6 counted values match the values of 8 bit compare registers 50 and 60 CR50 and CR60 TM5 and TM6 are cleared to 0 and the interrupt request signals INTTM5 and INTTM6 are generated Figure 6 10 8 Bit Timer Mode Control Register Setting for External Event Counter Operation Remarks 1 n 5 6 2 don t care Figure 6 11 External Event Counter Operation Timings with Rising Edge Specification R...

Page 117: ...r 5 TMC5 or bit 1 TMC61 and bit 0 TOE6 of 8 bit timer mode control register 6 TMC6 to 1 This enables a square wave of any selected frequency to be output Figure 6 12 8 Bit Timer Mode Control Register Settings for Square Wave Output Operation Caution When TI5 P100 TO5 or TI6 P101 TO6 pin is used as the timer output set 0 to port mode register PM100 or PM101 and output latch P100 or P101 Remark n 5 ...

Page 118: ... 1 fX 213 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 213 1 fX 214 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 1 fX 28 1 fX 215 1 fX 216 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 1 fX 29 1 fX 216 1 fX 217 1 f...

Page 119: ...er mode control register 6 TMC6 This PWM pulse has an 8 bit resolution The pulse can be converted into an analog voltage by integrating it with an external low pass filter LPF Count clock of 8 bit timer register 5 TM5 can be selected with timer clock select register 5 TCL5 and count clock of 8 bit timer register 6 TM6 can be selected with timer clock select register 6 TCL6 PWM output enable disabl...

Page 120: ... CRn0 00H active high setting Remark n 5 6 Count Clock TMn Count Value CRn0 TCEn INTTMn TOn 01 02 FF 00 01 02 N N 1 N 2 N 3 00 OVFn M N N 00 Inactive Level CRn0 Changing M N Active Level Inactive Level Inactive Level Count Clock TMn Count Value CRn0 TCEn INTTMn TOn 01 02 FF 00 01 02 FF 00 01 02 00 OVFn M 00 00 00 Inactive Level CRn0 Changing M 00 Inactive Level ...

Page 121: ...igure 6 16 PWM Output Operation Timings CRn0 FFH active high setting Remark n 5 6 Count Clock TMn Count Value CRn0 TCEn INTTMn TOn 01 02 FF 00 01 02 FF 00 01 02 00 OVFn FF FF FF 00 Inactive Level Inactive Level Active Level Inactive Level Active Level ...

Page 122: ...gh setting Caution If CRn0 is changed during TMn operation the value changed is not reflected until TMn overflows Remark n 5 6 Count Clock TMn Count Value CRn0 TCEn INTTMn TOn OVFn Active Level Inactive Level 00 FF N 2 N 1 N 02 01 00 FF N N 01 02 M M M 2 M 1 M M 3 00 Active Level Inactive Level CRn0 Changing N M ...

Page 123: ...ynchronously with the count pulse Figure 6 18 8 Bit Timer Registers 5 and 6 Start Timing Count Pulse TM5 TM6 Count Value 00H 01H 02H 03H 04H Timer Start TI5 TI6 Input CR50 CR60 TM5 TM6 Count Value TO5 TO6 Interrupt Request Flag 00H 00H 00H 00H 00H 2 8 bit compare register 50 and 60 setting The 8 bit compare registers 50 and 60 CR50 and CR60 can be set to 00H Thus when these 8 bit compare registers...

Page 124: ...gisters 50 and 60 CR50 and CR60 are changed are smaller than those of 8 bit timer registers 5 and 6 TM5 and TM6 TM5 and TM6 continue counting overflow and then restart counting from 0 Thus if the value M after CR50 and CR60 change is smaller than value N before the change it is necessary to restart the timer after changing CR50 and CR60 Figure 6 20 Timing after Compare Register Change during Timer...

Page 125: ...102 CHAPTER 6 8 BIT TIMER EVENT COUNTERS 5 AND 6 MEMO ...

Page 126: ...t request or RESET can be generated Table 7 1 Watchdog Timer Overrun Detection Times Runaway Detection Time MCS 1 MCS 0 211 1 fXX 211 1 fX 410 µs 212 1 fX 819 µs 212 1 fXX 212 1 fX 819 µs 213 1 fX 1 64 ms 213 1 fXX 213 1 fX 1 64 ms 214 1 fX 3 28 ms 214 1 fXX 214 1 fX 3 28 ms 215 1 fX 6 55 ms 215 1 fXX 215 1 fX 6 55 ms 216 1 fX 13 1 ms 216 1 fXX 216 1 fX 13 1 ms 217 1 fX 26 2 ms 217 1 fXX 217 1 fX ...

Page 127: ... 213 1 fX 1 64 ms 214 1 fX 3 28 ms 214 1 fXX 214 1 fX 3 28 ms 215 1 fX 6 55 ms 215 1 fXX 215 1 fX 6 55 ms 216 1 fX 13 1 ms 216 1 fXX 216 1 fX 13 1 ms 217 1 fX 26 2 ms 217 1 fXX 217 1 fX 26 2 ms 218 1 fX 52 4 ms 219 1 fXX 219 1 fX 104 9 ms 220 1 fX 209 7 ms Remarks 1 fXX Main system clock frequency fX or fX 2 2 fX Main system clock oscillation frequency 3 MCS Oscillation mode selection register OSM...

Page 128: ...3 WDTM4 WDTM3 8 Bit Counter TMMK4 RUN TMIF4 INTWDT Maskable Interrupt Request INTWDT Non Maskable Interrupt Request RESET Control Circuit 7 2 Watchdog Timer Configuration The watchdog timer consists of the following hardware Table 7 3 Watchdog Timer Configuration Item Configuration Timer clock select register 2 TCL2 Watchdog timer mode register WDTM Figure 7 1 Watchdog Timer Block Diagram Control ...

Page 129: ...timer Timer clock select register 2 TCL2 Watchdog timer mode register WDTM 1 Timer clock select register 2 TCL2 This register sets the watchdog timer count clock TCL2 is set with 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the watchdog timer count clock TCL2 sets the buzzer output frequency ...

Page 130: ...0 1 TCL27 TCL26 TCL25 Buzzer output disable fXX 29 fXX 210 fXX 211 Setting prohibited MCS 1 fX 29 9 8 kHz fX 210 4 9 kHz fX 211 2 4 kHz MCS 0 fX 210 4 9 kHz fX 211 2 4 kHz fX 212 1 2 kHz Buzzer Output Frequency Selection 625 kHz 313 kHz 156 kHz 78 1 kHz 39 1 kHz 19 5 kHz 9 8 kHz 2 4 kHz 313 kHz 156 kHz 78 1 kHz 39 1 kHz 19 5 kHz 9 8 kHz 4 9 kHz 1 2 kHz Caution 1 When rewriting TCL2 to other data s...

Page 131: ...s counting WDTM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets WDTM to 00H Figure 7 3 Watchdog Timer Mode Register Format Notes 1 Once set to 1 WDTM3 and WDTM4 cannot be cleared to 0 by software 2 The watchdog timer starts operating as an interval timer as soon as RUN has been set to 1 3 Once set to 1 RUN cannot be cleared to 0 by software Thus once counting starts i...

Page 132: ... 1 the watchdog timer can be cleared The watchdog timer continues operating in the HALT mode but it stops in the STOP mode Thus set RUN to 1 before the STOP mode is set clear the watchdog timer and then execute the STOP instruction Caution The actual overrun detection time may be shorter than the set time by a maximum of 0 5 Table 7 4 Watchdog Timer Overrun Detection Time TCL22 TCL21 TCL20 Runaway...

Page 133: ...UN of WDTM to 1 before the STOP mode is set clear the interval timer and then execute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 with the watchdog timer mode selected the interval timer mode is not set unless RESET input is applied 2 The interval time just after setting with WDTM may be shorter than the set time by a maximum of 0 5 Table 7 5 Interval Timer Interval Time T...

Page 134: ...procedure below to output clock pulses 1 Select the clock pulse output frequency with clock pulse output disabled with bits 0 to 3 TCL00 to TCL03 of TCL0 2 Set the P35 output latch to 0 3 Set bit 5 PM35 of port mode register 3 to 0 set to output mode 4 Set bit 7 CLOE of timer clock select register 0 to 1 Caution Clock output cannot be used when setting P35 output latch to 1 Remark When clock outpu...

Page 135: ...ntrol Circuit Configuration Item Configuration Timer clock select register 0 TCL0 Port mode register 3 PM3 Figure 8 2 Clock Output Control Circuit Block Diagram Control register Internal Bus fXX fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 CLOE TCL03 TCL02 TCL01 TCL00 P35 Output Latch Synchronizing Circuit 4 PM35 Selector Timer Clock Select Register 0 Port Mode Register 3 PCL P35 ...

Page 136: ...fXX fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 Setting prohibited MCS 1 fX 5 0 MHz fX 2 2 5 MHz fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz MCS 0 fX 2 2 5 MHz fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz PCL Output Clock Selection CLOE 0 1 PCL Output Control Output disable Output enable TCL00 1...

Page 137: ...de Selection n 0 to 7 Output mode output buffer ON Input mode output buffer OFF 2 Port mode register 3 PM3 This register set port 3 input output in 1 bit units When using the P35 PCL pin for clock output function set PM35 and output latch of P35 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 8 4 Port Mode Register 3 Format ...

Page 138: ...tput from the BUZ P36 pin Follow the procedure below to output the buzzer frequency 1 Select the buzzer output frequency with bits 5 to 7 TCL25 to TCL27 of TCL2 2 Set the P36 output latch to 0 3 Set bit 6 PM36 of port mode register 3 to 0 Set to output mode Caution Buzzer output cannot be used when setting P36 output latch to 1 9 2 Buzzer Output Control Circuit Configuration The buzzer output cont...

Page 139: ...he buzzer output function Timer clock select register 2 TCL2 Port mode register 3 PM3 1 Timer clock select register 2 TCL2 This register sets the buzzer output frequency TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the buzzer output frequency TCL2 sets the watchdog timer count clock ...

Page 140: ... 1 1 0 1 0 1 TCL27 TCL26 TCL25 Buzzer output disable fXX 29 fXX 210 fXX 211 Setting prohibited MCS 1 fX 29 9 8 kHz fX 210 4 9 kHz fX 211 2 4 kHz MCS 0 fX 210 4 9 kHz fX 211 2 4 kHz fX 212 1 2 kHz Buzzer Output Frequency Selection 625 kHz 313 kHz 156 kHz 78 1 kHz 39 1 kHz 19 5 kHz 9 8 kHz 2 4 kHz 313 kHz 156 kHz 78 1 kHz 39 1 kHz 19 5 kHz 9 8 kHz 4 9 kHz 1 2 kHz Cautions 1 When rewriting TCL2 to ot...

Page 141: ...e Selection n 0 to 7 Output mode output buffer ON Input mode output buffer OFF 2 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P36 BUZ pin for buzzer output function set PM36 and output latch of P36 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 9 3 Port Mode Register 3 Format ...

Page 142: ...alog input from ANI0 to ANI7 and perform A D conversion As for A D conversion operations when the hardware is started up the A D conversion operation stops when A D conversion is completed and an interrupt request INTAD is generated In the case of software start the A D conversion operation is repeated Each time an A D conversion operation ends an interrupt request INTAD is generated 10 2 A D Conv...

Page 143: ...P12 ANI3 P13 ANI4 P14 ANI5 P15 ANI6 P16 ANI7 P17 Selector A D Converter Mode Register 3 Trigger Enable ES40 ES41Note 3 Sample Hold Circuit CS ADIS3 4 Internal Bus Internal Bus Edge Detector Control Circuit Series Resistor String AVDD Voltage Comparator Tap Selector INTAD INTP3 Successive Approximation Register SAR A D Converter Input Select Register ADIS2 ADIS1 ADIS0 Note 1 Note 2 INTP3 P03 TRG FR...

Page 144: ...s resistor string is connected within AVREF to AVSS and generates a voltage for comparison with the analog input 6 ANI0 to ANI7 pins These are 8 channel analog input pins to input analog signals to undergo A D conversion to the A D converter Pins other than those selected as analog input by the A D converter input select register ADIS can be used as input output ports Caution Use ANI0 to ANI7 inpu...

Page 145: ...rter mode register ADM A D converter input select register ADIS External interrupt mode register 1 INTM1 1 A D converter mode register ADM This register sets the analog input channel for A D conversion conversion time conversion start stop and external trigger ADM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADM to 01H ...

Page 146: ... 2 1 0 FF80H Address ADM Symbol ADM2 ADM1 HSC 5 01H After Reset R W R W ADM3 0 0 0 0 1 1 1 1 ADM2 0 0 1 1 0 0 1 1 ADM1 0 1 0 1 0 1 0 1 Analog Input Channel Selection ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 TRG 0 1 External Trigger Selection No external trigger software starts Conversion started by external trigger hardware starts FR1 0 0 1 1 FR0 0 1 0 0 Other than above A D Conversion Time Selecti...

Page 147: ...ls set for analog input with ADIS 2 No internal pull up resistor can be used to the channels set for analog input with ADIS irrespective of the value of bit 1 PUO1 of the pull up resistor option register L PUOL Figure 10 3 A D Converter Input Select Register Format 0 7 0 6 0 0 4 ADIS3 3 2 1 0 FF84H Address ADIS Symbol ADIS2 ADIS1 ADIS0 5 00H After Reset R W R W ADIS3 0 0 0 0 0 0 0 0 1 Other than a...

Page 148: ...ipulation instruction RESET input sets INTM1 to 00H Figure 10 4 External Interrupt Mode Register 1 Format 0 7 0 6 0 0 4 0 3 2 1 0 FFEDH Address INTM1 Symbol 0 ES41 ES40 5 00H After Reset R W R W ES41 0 0 1 1 ES40 0 1 0 1 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges Caution Set 0 to the bits 2 to 7 ...

Page 149: ...g voltage tap and the analog input is compared by the voltage comparater If the analog input is larger than 1 2 AVREF the MSB of the SAR remains set If it is smaller than 1 2 AVREF the MSB is reset 7 Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison In this case the series resistor string voltage tap is selected according to the preset value of bit 7 as descr...

Page 150: ... 10 5 A D Converter Basic Operation A D conversion operations are performed continuously until bit 7 CS of A D converter mode register ADM is reset 0 by software If a write to the ADM is performed during an A D conversion operation the conversion operation is initialized and if the CS bit is set 1 conversion starts again from the beginning After RESET input the value of ADCR is undefined ...

Page 151: ...CR 0 5 Where INT Function which returns integer parts of value in parentheses VIN Analog input voltage AVREF AVREF pin voltage ADCR Value of A D conversion result register ADCR Figure 10 6 shows the relation between the analog input voltage and the A D conversion result Figure 10 6 Relations between Analog Input Voltage and A D Conversion Result VIN AVREF AVREF 256 AVREF 256 1 512 1 256 3 512 2 25...

Page 152: ...ter mode register ADM are set to 1 the A D conversion standby state is set When the external trigger signal INTP3 is input the A D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 ADM1 to ADM3 of ADM Upon termination of the A D conversion the conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is ...

Page 153: ... of the A D conversion the conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is generated After one A D conversion operation is started and terminated the next A D conversion operation starts immediately The A D conversion operation con tinues repeatedly until new data is written to ADM If data with CS set to 1 is written to ADM again dur...

Page 154: ...ever there is no precision to the actual AVREF voltage and therefore the conversion values themselves lack precision and can only be used for relative comparison Figure 10 9 Example of Method of Reducing Current Dissipation in Standby Mode 2 Input range of ANI0 to ANI7 The input voltages of ANI0 to ANI7 should be within the specification range In particular if a voltage above AVREF or below AVSS i...

Page 155: ...reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable due to coupling noise Therefore avoid applying pulses to pins adjacent to the pin undergoing A D conversion 5 AVREF pin input impedance A series resistor string of approximately 10 kΩ is connected between the AVREF...

Page 156: ...fore the ADM rewrite and when ADIF is read immediately after the ADM rewrite ADIF may be set despite the fact that the A D conversion for the post change analog input has not ended When the A D conversion is stopped and then resumed clear the ADIF before it is resumed Figure 10 11 A D Conversion End Interrupt Request Generation Timing 7 AVDD pin The AVDD pin is the analog circuit power supply pin ...

Page 157: ...134 CHAPTER 10 A D CONVERTER MEMO ...

Page 158: ...n the baud rate can be defined by scaling the input clock to the ASCK pin The MIDI standard baud rate 31 25 kbps can be used by employing the dedicated UART baud rate generator 3 3 wire serial I O mode MSB first LSB first switchable In this mode 8 bit data transfer is performed using three lines the serial clock SCK2 and serial data lines SI2 SO2 In the 3 wire serial I O mode simultaneous transmis...

Page 159: ...e 11 1 Serial Interface Channel 2 Configuration Item Configuration Register Transmit shift register TXS Receive shift register RXS Receive buffer register RXB Control register Serial operating mode register 2 CSIM2 Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Baud rate generator control register BRGC ...

Page 160: ...22 CSCK INTSER SCK Output Control Circuit Baud Rate GeneratorNote fxx fxx 210 Internal Bus CSCK SCK INTST Baud Rate Generator Control Register Serial Operating Mode Register 2 PE FE OVE Transmission Control Circuit PM71 ISRM ASCK SCK2 P72 PM72 Direction Control Circuit Transmit Shift Register TXS SIO2 RXE PS1 PS0 CL SL ISRM TXE SCK 4 4 CSIE2 TXE RXE MDL3 MDL2 MDL1 MDL0 TPS3 TPS2 TPS1 TPS0 Figure 1...

Page 161: ...r Control Register 4 TXE CSIE2 5 Bit Counter Selector Selector Decoder 1 2 Selector Transmit Clock 1 2 Selector Receive Clock Match Match MDL0 MDL3 5 Bit Counter RXE Start Bit Detection Selector fxx fxx 210 TPS0 TPS3 SCK CSCK ASCK SCK2 P72 4 4 Start Bit Sampling Clock Figure 11 2 Baud Rate Generator Block Diagram ...

Page 162: ...ive data Each time one byte of data is received new receive data is transferred from the receive shift register RXS If the data length is specified as 7 bits the receive data is transferred to bits 0 to 6 of RXB and the MSB of RXB is always set to 0 RXB is read with an 8 bit memory manipulation instruction It cannot be written to RXB value is FFH after RESET input Caution RXB and the transmit shif...

Page 163: ... is used in the 3 wire serial I O mode CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H Figure 11 3 Serial Operating Mode Register 2 Format Cautions 1 Set 0 to the bits 0 and 3 to 6 2 When UART mode is selected CSIM2 should be set to 00H 6 5 4 3 2 1 0 7 Symbol CSIM2 CSIE2 0 0 0 0 CSIM 22 CSCK 0 FF72H 00H R W Address After Reset R W CSCK 0 1 Clock Sel...

Page 164: ...XE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled PS1 0 1 0 1 bit 1 2 bits 0 Parity Bit Specification No Parity Even parity PS0 0 1 0 parity always added in transmission No parity test in reception parity error not generated 0 1 1 Odd parity 0 Note When SCK is set to 1 and the baud rate generator output is selected the ASCK pin can be used as an input output p...

Page 165: ...ns P70 SI2 RxD Pin Functions Shift Clock Start Bit TXE RXE SCK CSIE2 CSIM22 CSCK PM70 P70 PM71 P71 PM72 P72 ASIM CSIM2 0 0 0 1 1 0 1 0 1 0 1 1 Note2 x Note2 0 1 1 0 1 0 x 1 x 1 MSB LSB External clock Internal clock External clock Internal clock SI2 SO2 CMOS output SCK2 input SCK2 output SCK2 input SCK2 output Other than above Setting prohibited Note2 P72 SCK2 ASCK Pin Functions P71 SO2 TxD Pin Fun...

Page 166: ...s 1 The receive buffer register RXB must be read when an overrun error is generated Overrun errors will continue to be generated until RXB is read 2 Even if the stop bit length has been set as 2 bits by bit 2 SL of the asynchronous serial interface mode register ASIM only single stop bit detection is performed during reception 3 Asynchronous serial interface status register ASIS This is a register...

Page 167: ... fSCK 30 fSCKNote 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 5 4 3 2 1 0 7 Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R W Address After Reset R W k 4 Baud rate generator control register BRGC This register sets the serial clock for serial interface channel 2 BRGC is set with an 8 bit memory manipulation instruction RESET input sets BRGC to 00H Figure 11 6 Baud Rate Generator Control R...

Page 168: ... 1 1 fXX 26 fX 26 78 1 kHz fX 27 39 1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above Setting prohibited Caution When a write is performed to BRGC during a communication operation baud rate generator output is disrupted and communication cannot be performed normally Therefore BRGC mus...

Page 169: ...L0 to MDL3 0 k 14 Table 11 3 Relation between Main System Clock and Baud Rate fx 5 0 MHz fx 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error 75 00H 1 73 0BH 1 14 EBH 1 14 110 06H 0 88 E6H 0 88 03H 2 01 E3H 2 01 150 00H 1 73 E0H 1 73 EBH 1 14 DBH 1 14 300 E0H 1 73 D0H 1 73 DBH 1 14 CBH 1 14 600 D0H 1 73 C0H 1 73 CBH 1 14 BBH 1 14 1...

Page 170: ...om the ASCK pin is obtained with the following expression Baud rate Hz where fASCK Frequency of clock input to ASCK pin k Value set in MDL0 to MDL3 0 k 14 Table 11 4 Relation between ASCK Pin Input Frequency and Baud Rate When BRGC is set to 00H Baud Rate bps ASCK Pin Input Frequency 75 2 4 kHz 110 3 52 kHz 150 4 8 kHz 300 9 6 kHz 600 19 2 kHz 1200 38 4 kHz 2400 76 8 kHz 4800 153 6 kHz 9600 307 2 ...

Page 171: ...P71 SO2 TxD and P72 SCK2 ASCK pins can be used as normal input output ports 1 Register setting Operation stop mode settings are performed using serial operating mode register 2 CSIM2 and the asynchronous serial interface mode register ASIM a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H CSIM 22 6 5 4 3 2 1 0 ...

Page 172: ...Reset R W RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled b Asynchronous serial interface mode register ASIM ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM to 00H ...

Page 173: ... UART baud rate generator is incorporated allowing communication over a wide range of baud rates In addition the baud rate can be defined by scaling the input clock to the ASCK pin The MIDI standard baud rate 31 25 kbps can be used by employing the dedicated UART baud rate generator 1 Register setting UART mode settings are performed using serial operating mode register 2 CSIM2 the asynchronous se...

Page 174: ...lock from off chip to ASCK pin Dedicated baud rate generator outputNote ISRM 0 1 Control of Reception Completion Interrupt in Case of Error Generation Reception completion interrupt request generated in case of error generation Reception completion interrupt request not generated in case of error generation SL Transmit Data Stop Bit Length Specification CL 1 Character Length Specification 7 bits 8...

Page 175: ... detected PE 0 1 Parity Error Flag Parity error not generated Parity error generated When transmit data parity does not match c Asynchronous serial interface status register ASIS ASIS is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIS to 00H Notes 1 The receive buffer register RXB must be read when an overrun error is generated Overrun errors will continue to be gen...

Page 176: ...CK 19 fSCK 20 fSCK 21 fSCK 22 fSCK 23 fSCK 24 fSCK 25 fSCK 26 fSCK 27 fSCK 28 fSCK 29 fSCK 30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 5 4 3 2 1 0 7 Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R W Address After Reset R W k d Baud rate generator control register BRGC BRGC is set with an 8 bit memory manipulation instruction RESET input sets BRGC to 00H Remark fSCK 5 bit counter source...

Page 177: ...7 39 1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above Setting prohibited Caution When a write is performed to BRGC during a communication operation baud rate generator output is disrupted and communication cannot be performed normally Therefore BRGC must not be written to during a co...

Page 178: ...MDL0 to MDL3 0 k 14 Table 11 5 Relation between Main System Clock and Baud Rate fx 5 0 MHz fx 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error 75 00H 1 73 0BH 1 14 EBH 1 14 110 06H 0 88 E6H 0 88 03H 2 01 E3H 2 01 150 00H 1 73 E0H 1 73 EBH 1 14 DBH 1 14 300 E0H 1 73 D0H 1 73 DBH 1 14 CBH 1 14 600 D0H 1 73 C0H 1 73 CBH 1 14 BBH 1 14...

Page 179: ...om the ASCK pin is obtained with the following expression Baud rate Hz where fASCK Frequency of clock input to ASCK pin k Value set in MDL0 to MDL3 0 k 14 Table 11 6 Relation between ASCK Pin Input Frequency and Baud Rate When BRGC is set to 00H Baud Rate bps ASCK Pin Input Frequency 75 2 4 kHz 110 3 52 kHz 150 4 8 kHz 300 9 6 kHz 600 19 2 kHz 1200 38 4 kHz 2400 76 8 kHz 4800 153 6 kHz 9600 307 2 ...

Page 180: ...t length for each data frame is carried out with asynchronous serial interface mode register ASIM When 7 bits are selected as the number of character bits only the lower 7 bits bits 0 to 6 are valid in transmission the most significant bit bit 7 is ignored and in reception the most significant bit bit 7 is always 0 The serial transfer rate is selected by means of the ASIM and the baud rate generat...

Page 181: ...a is counted If it is odd a parity error occurs ii Odd parity Transmission Conversely to the situation with even parity the number of bits with a value of 1 including the parity bit in the transmit data is controlled to be odd The value of the parity bit is as follows Number of bits with a value of 1 in transmit data is odd 0 Number of bits with a value of 1 in transmit data is even 1 Reception Th...

Page 182: ...nsmission completion interrupt request INTST is generated Figure 11 8 Asynchronous Serial Interface Transmission Completion Interrupt Request Timing a Stop bit length 1 b Stop bit length 2 Caution Rewriting of the asynchronous serial interface mode register ASIM should not be performed during a transmit operation If rewriting of the ASIM register is performed during transmission subsequent transmi...

Page 183: ...is performed When character data a parity bit and one stop bit are detected after the start bit reception of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to the receive buffer register RXB and a reception completion interrupt request INTSR is generated If an error is generated the receive data in which the error was generated...

Page 184: ...the receive buffer register RXB or receiving the next data if there is an error in the next data the corresponding error flag is set Table 11 7 Receive Error Causes Receive Errors Cause Parity error Transmission time parity specification and reception data parity do not match Framing error Stop bit not detected Overrun error Reception of next data is completed before data is read from receive regi...

Page 185: ...d during reception enable disable will differ depending on the timing the condition of the receive buffer register RXB and generation of the reception completed interrupt request INTSR The timing is displayed in Figure 11 11 Figure 11 11 State of the Receive Buffer Register RXB when Reception is Interrupted and Generation Non Generation of an Interrupt Request INTSR When RXE is set to 0 at a time ...

Page 186: ...erial operating mode register 2 CSIM2 the asynchro nous serial interface mode register ASIM and the baud rate generator control register BRGC a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H Caution Set 0 to the bits 0 and 3 to 6 6 5 4 3 2 1 0 7 Symbol CSIM2 CSIE2 0 0 0 0 CSIM 22 CSCK 0 CSCK 0 1 Clock Selectio...

Page 187: ... 0 1 Control of Reception Completion Interrupt in Case of Error Generation Reception completion interrupt request generated in case of error generation Reception completion interrupt request not generated in case of error generation SL Transmit Data Stop Bit Length Specification CL 1 Character Length Specification 7 bits 8 bits RXE 0 1 Receive Operation Control Receive operation stopped Receive op...

Page 188: ...fSCK 19 fSCK 20 fSCK 21 fSCK 22 fSCK 23 fSCK 24 fSCK 25 fSCK 26 fSCK 27 fSCK 28 fSCK 29 fSCK 30 fSCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 5 4 3 2 1 0 7 Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R W Address After Reset R W k c Baud rate generator control register BRGC BRGC is set with an 8 bit memory manipulation instruction RESET input sets BRGC to 00H continued Remark fSCK 5 b...

Page 189: ...7 39 1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above Setting prohibited Caution When a write is performed to BRGC during a communication operation baud rate generator output is disrupted and communication cannot be performed normally Therefore BRGC must not be written to during a co...

Page 190: ...MDL0 to MDL3 to 1 1 1 1 The serial clock frequency becomes the same as the source clock frequency for the 5 bit counter ii When the baud rate generator is used Select a serial clock frequency with TPS0 TPS3 Be sure then to set MDL0 to MDL3 to 1 1 1 1 The serial clock frequency is calculated by the following formula Serial clock frequency Hz Remarks 1 fX Main system clock oscillation frequency 2 fX...

Page 191: ...n transmit data is held in the SO2 latch and output from the SO2 pin Also receive data input to the SI2 pin is latched in the receive buffer register RXB SIO2 on the rise of SCK2 At the end of an 8 bit transfer the operation of the TXS SIO2 or RXS stops automatically and the interrupt request flag SRIF is set Figure 11 12 3 Wire Serial I O Mode Timing 3 MSB LSB switching as the start bit The 3 wir...

Page 192: ... transfer data to the transmission shift register TXS SIO2 when the following two conditions are satisfied Serial interface channel 2 operation control bit CSIE2 1 Internal serial clock is stopped or SCK2 is a high level after 8 bit serial transfer Caution If CSIE2 is set to 1 after data write to TXS SIO2 transfer does not start Upon termination of 8 bit transfer serial transfer automatically stop...

Page 193: ...170 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 MEMO ...

Page 194: ...ask control Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register PR0L PR0H PR1L Multiple high priority interrupts can be applied to low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupts has a predetermined priority see Table 12 1 A stan...

Page 195: ...l 0018H B error generation 5 INTSR End of serial interface channel 2 001AH UART reception INTCSI2 End of serial interface channel 2 3 wire transfer 6 INTST End of serial interface channel 2 001CH UART transfer 7 INTAD End of A D converter conversion 0028H 8 INTTM5 Generation of 8 bit timer event 002AH counter 5 match signal 9 INTTM6 Generation of 8 bit timer event 002CH counter 6 match signal Soft...

Page 196: ...ol Circuit Vector Table Address Generator Standby Release Signal Internal Bus Priority Control Circuit Vector Table Address Generator Standby Release Signal Interrupt Request Figure 12 1 Basic Configuration of Interrupt Function 1 2 A Internal non maskable interrupt B Internal maskable interrupt ...

Page 197: ...tector Interrupt Request IE PR ISP MK IF Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus Figure 12 1 Basic Configuration of Interrupt Function 2 2 C External maskable interrupt D Software interrupt Remark IF Interrupt request flag IE Interrupt enable flag ISP Inservice priority flag MK Interrupt mask flag PR Priority specify flag ...

Page 198: ...a listing of interrupt request flags interrupt mask flags and priority specify flags corresponding to interrupt request sources Table 12 2 Various Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specify Flag Register Register Register INTWDT TMIF4 IF0L TMMK4 MK0L TMPR4 PR0L INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PM...

Page 199: ...upon acknowledgment of an interrupt request or upon application of RESET input IF0L IF0H and IF1L are set with a 1 bit or 8 bit memory manipulation instruction If IF0L and IF0H are used as a 16 bit register IF0 use a 16 bit memory manipulation instruction for the setting RESET input sets these registers to 00H Figure 12 2 Interrupt Request Flag Register Format 7 0 Symbol IF0L 6 0 5 0 4 PIF3 3 PIF2...

Page 200: ...L MK0H MK1L The interrupt mask flag is used to enable disable the corresponding maskable interrupt service and to set standby clear enable disable MK0L MK0H and MK1L are set with a 1 bit or 8 bit memory manipulation instruction If MK0L and MK0H are used as a 16 bit register MK0 use a 16 bit memory manipulation instruction for the setting RESET input sets these registers to FFH Figure 12 3 Interrup...

Page 201: ...R1L are set with a 1 bit or 8 bit memory manipulation instruction If PR0L and PR0H are used as a 16 bit register PR0 use a 16 bit memory manipulation instruction for the setting RESET input sets these registers to FFH Figure 12 4 Priority Specify Flag Register Format 7 1 Symbol PR0L 6 1 5 1 4 PPR3 3 PPR2 2 PPR1 1 1 0 TMPR4 Address FFE8H FFH After Reset R W R W 0 1 Priority Level Selection High pri...

Page 202: ... FFECH 00H After Reset R W R W 7 ES31 Symbol INTM0 6 ES30 5 ES21 4 ES20 3 0 2 0 1 0 0 0 0 0 1 1 INTP1 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES21 0 1 0 1 ES20 0 0 1 1 INTP2 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES31 0 1 0 1 ES30 Caution Set 0 to the bits 2 to 7 Address FFEDH 00H After R...

Page 203: ... the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag The contents of PSW are also saved to the stack by the PUSH PSW instruction It is reset from the stack with the RETI RETB and POP PSW instructions RESET input sets PSW to 02H Figure 12 7 Program Status Word Configuration ...

Page 204: ...equest generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program is terminated following RETI instruction execution and one main routine instruction is executed If a new non maskable interrupt request is generated twice or more during non maskable interrupt service program execution only one ...

Page 205: ... Interval timer Start No Yes Yes No Yes No Yes No Yes No Figure 12 8 Flowchart from Non Maskable Interrupt Request Generation to Acknowledgment WDTM Watchdog timer mode register WDT Watchdog timer Figure 12 9 Non Maskable Interrupt Request Acknowledge Timing TMIF4 Watchdog timer interrupt request flag Instruction Instruction CPU Instruction TMIF4 PSW and PC Save Jump to Interrupt Servicing Interru...

Page 206: ...non maskable interrupt servicing program execution Main Routine NMI Request 1 Instruction Execution NMI Request NMI Request Execute NMI Request Reserve Reserved NMI Request Processing Main Routine NMI Request 1 Instruction Execution NMI Request NMI Request Execute NMI Request Reserve NMI Request Reserve Reserved NMI Request Processing Cannot acknowledge NMI Request Although multiple NMI requests m...

Page 207: ...interrupt request is generated just before a divide instruction the wait time is maximized Remark 1 clock fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request specified for higher priority with the priority specify flag is acknowledged first Also when the same priority is specified with the priority specify flag the interrupt request with the higher de...

Page 208: ...erve Interrupt request reserve Vectored interrupt servicing IE 1 Yes High priority Yes No Yes No No No Yes Interrupt Request Generation No Yes No Low Priority Yes Yes No Yes Yes No No Do any of the simultaneously generated PR 0 interrupt requests have a high priority IF Interrupt request flag MK Interrupt mask flag PR Priority specify flag IE Flag which controls maskable interrupt request acknowle...

Page 209: ...ximum Time Remark 1 clock fCPU CPU clock fCPU 1 fCPU 1 Instruction Instruction PSW and PC Save Jump to Interrupt Servicing 6 Clocks Interrupt Servicing Program 8 Clocks 7 Clocks CPU Processing IF PR 1 IF PR 0 Instruction Divide Instruction PSW and PC Save Jump to Interrupt Servicing 6 Clocks Interrupt Servicing Program 33 Clocks 32 Clocks CPU Processing IF PR 1 IF PR 0 25 Clocks ...

Page 210: ...ary during interrupt processing to set the IE flag 1 using the IE instruction and enable interrupts There are cases where multiple requests are not enabled even though interrupts are enabled However this is controlled by the priority of the interrupt There are two interrupt priorities the default priority and the programmable priority Multiple interrupt control is handled by programmable priority ...

Page 211: ...upt enable 2 D Multiple interrupt disable 3 ISP and IE are the flags contained in PSW ISP 0 An interrupt with higher priority is being serviced ISP 1 An interrupt request is not accepted or an interrupt with lower priority is being serviced IE 0 Interrupt request acknowledge is disabled IE 1 Interrupt request acknowledge is enabled 4 PR is a flag contained in PR0L PR0H and PR1L PR 0 Higher priorit...

Page 212: ...pt INTxx and a multiple interrupt is generated Before each interrupt request is acknowledged the EI instruction is always executed and interrupt request acknowledgment enabled Example 2 Example of when a multiple interrupt is not generated because of priority control Interrupt request INTyy which has been generated during processing of interrupt INTxx and which has an interrupt priority that is lo...

Page 213: ...e interrupt is not generated because interrupts are not enabled Because interrupts are not enabled the EI instruction is not executed during processing of interrupt INTxx interrupt request INTyy is not acknowledged and a multiple interrupt is not generated Interrupt request INTyy is reserved and acknowledged after one main processing instruction is implemented PR 0 High priority level IE 0 Interru...

Page 214: ...R1 CY PSW bit SET1 PSW bit CLR1 PSW bit RETB RETI PUSH PSW POP PSW BT PSW bit addr16 BF PSW bit addr16 BTCLR PSW bit addr16 EI DI Manipulate instructions for IF0L IF0H IF1L MK0L MK0H MK1L PR0L PR0H PR1L INTM0 INTM1 registers Caution The BRK instruction is not one of the above interrupt request reserve instructions However in the case of software interrupts which are activated by execution of the B...

Page 215: ...st Hold Remarks 1 Instruction N Instruction that holds interrupts requests 2 Instruction M Instructions other than instruction N 3 The operation of IF interrupt request is not affected by PR priority level values CPU processing IF Instruction N Instruction M Save PSW and PC Jump to interrupt service Interrupt service program ...

Page 216: ...DD 1 8 V is possible Thus the STOP mode is effective to hold data memory contents with ultra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared select the HALT mode if it is necessary to start processin...

Page 217: ...TOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register OSTS OSTS is set with an 8 bit memory manipulation instruction RESET input sets OSTS to 04H However it takes 217 fX not 218 fX until the STOP mode is cleared by RESET input Figure 13 1 Oscillation Stabilization Time Select Register Format Caution The wait...

Page 218: ...n The operating status in the HALT mode is described below Table 13 1 HALT Mode Operating Status Item HALT Mode Operating Status Clock generator Can be oscillated Supply to the CPU clock is stopped CPU Operation stops Port Status before HALT mode setting is held 8 bit timer event counter 5 6 Operable Watchdog timer A D converter Serial interface External interrupt request ...

Page 219: ...upt service is carried out If disabled the next address instruction is executed Figure 13 2 HALT Mode Clear upon Interrupt Generation Remarks 1 The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged 2 Wait time will be as follows When vectored interrupt service is carried out 8 to 9 clocks When vectored interrupt service is not carried ou...

Page 220: ...ode Release Release Source MK PR IE ISP Operation Maskable interrupt 0 0 0 Next address instruction execution request 0 0 1 Interrupt service execution 0 1 0 1 Next address instruction execution 0 1 0 0 1 1 1 Interrupt service execution 1 HALT mode hold Non maskable interrupt Interrupt service execution request RESET input Reset processing Remark Don t care HALT Instruction RESET Signal Operating ...

Page 221: ...e standby mode is immediately cleared if set Thus the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction After the wait set using the oscillation stabilization time select register OSTS the operating mode is set The operating status in the STOP mode is described below Table 13 3 STOP Mode Operating Status Item STOP Mode Operating Status Clock generator Oscillat...

Page 222: ...s of sources a Release by unmasked interrupt request An unmasked interrupt request is used to release the STOP mode If interrupt acknowledge is enabled after the lapse of oscillation stabilization time vectored interrupt service is carried out If interrupt acknowledge is disabled the next address instruction is executed Figure 13 4 STOP Mode Release by Interrupt Generation Remark The broken line i...

Page 223: ... time reset operation is carried out Figure 13 5 Release by STOP Mode RESET Input Remarks 1 fX main system clock oscillation frequency 2 Values in parentheses when operated at fX 5 0 MHz Table 13 4 Operation after STOP Mode Release Release Source MK PR IE ISP Operation Maskable interrupt request 0 0 0 Next address instruction execution 0 0 1 Interrupt service execution 0 1 0 1 Next address instruc...

Page 224: ... to the status as shown in Table 14 1 Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear When a high level is input to the RESET input the reset is cleared and program execution starts after the lapse of oscillation stabilization time 217 fX The reset applied by watchdog timer overflow is automatically cleared after a reset and program ex...

Page 225: ...t Pin Delay Delay Hi Z X1 Normal Operation Reset Period Oscillation Stop Oscillation Stabilization Time Wait Normal Operation Reset Processing X1 Normal Operation Watchdog Timer Overflow Internal Reset Signal Port Pin Reset Period Oscillation Stop Oscillation Stabilization Time Wait Normal Operation Reset Processing Hi Z Figure 14 2 Timing of Reset Input by RESET Input Figure 14 3 Timing of Reset ...

Page 226: ...ry size switching register IMS Note3 Oscillation stabilization time select register OSTS 04H Timer clock selection register 0 TCL0 00H 8 bit timer event counter Timer register TM5 TM6 00H 5 and 6 Compare registers CR50 CR60 00H Clock select register TCL5 TCL6 00H Mode control registers TMC5 TMC6 00H Watchdog timer Clock select register TCL2 00H Mode register WDTM 00H Serial Interface Mode register...

Page 227: ...lag register PR0L PR0H PR1L FFH External interrupt mode register INTM0 INTM1 00H Notes 1 During reset input or oscillation stabilization time wait only the PC contents among the hardware statuses become undefined All other hardware statuses remains unchanged after reset 2 The post reset status is held in the standby mode 3 The values after reset depend on the product µPD78081 82H µPD78082 64H µPD7...

Page 228: ...peed RAM capacity 512 bytes µPD78081 256 bytes µPD78082 384 bytes Internal ROM and internal high speed Enable Note Disable RAM capacity change by internal memory size switching register IMS IC pin Not available Available VPP pin Available Not available Electrical specifications Refer to a data sheet of each product Note The internal PROM becomes 24 Kbytes and the internal expansion RAM becomes 512...

Page 229: ...hing register IMS By setting the IMS memory mapping can be made to match the memory mapping of the µPD78081 and 78082 which have different internal memory IMS is set with an 8 bit memory manipulation instruction RESET input sets IMS to 46H Figure 15 1 Memory Size Switching Register Format 7 RAM2 Symbol IMS 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H 46H After Reset R W R W 0 Intern...

Page 230: ... and a low level signal is applied to the RESET pin the µPD78P083 are set to the PROM programming mode This is one of the operating modes shown in Table 15 3 below according to the setting of the CE OE and PGM pins The PROM contents can be read by setting the read mode Table 15 3 PROM Programming Operating Modes Pin Operating mode Page data latch L 12 5 V 6 5 V H L H Data input Page write H H L Hi...

Page 231: ... write and verify operations are executed X times X 10 6 Byte write mode A byte write is executed by applying a 0 1 ms program pulse active low to the PGM pin while CE L and OE H After this program verification can be performed by setting OE to L If programming is not performed by one program pulse repeated write and verify operations are executed X times X 10 7 Program verify mode Setting CE to L...

Page 232: ...5 V X 0 Latch Address Address 1 Latch Address Address 1 Latch Address Address 1 Latch X X 1 0 1 ms program pulse Verify 4 Bytes Pass Address N No Pass VDD 4 5 to 5 5 V VPP VDD All bytes verified End of write Address Address 1 No Yes X 10 Fail Fail Yes All Pass Defective product Remark G Start address N Last address of program ...

Page 233: ...CHAPTER 15 µPD78P083 Figure 15 3 Page Program Mode Timing Page Data Latch Page Program Program Verify Data Input Data Output A2 A14 A0 A1 D0 D7 VPP VDD VPP VDD 1 5 VDD VDD VIH CE PGM OE VIL VIH VIL VIH VIL ...

Page 234: ...t Address G VDD 6 5 V VPP 12 5 V X 0 X X 1 0 1 ms program pulse Verify Address N VDD 4 5 to 5 5 V VPP VDD All bytes verified End of write Fail Fail Pass Yes All Pass No Pass Defective product No Yes X 10 Address Address 1 Remark G Start address N Last address of program ...

Page 235: ...g VPP 2 VPP must not exceed 13 5 V including overshoot voltage 3 Disconnecting inserting the device from to the on board socket while 12 5 V is being applied to the VPP pin may have an adverse affect on device reliability A0 A14 D0 D7 Program Program Verify Data Input Data Output VPP VDD VDD 1 5 VDD VIH VIL VIH VIL VIH VIL VPP VDD CE PGM OE ...

Page 236: ...e handled as shown in paragraph 2 PROM programming mode in section 1 5 Pin Configuration Top View 2 Supply 5 V to the VDD and VPP pins 3 Input the address of data to be read to pins A0 through A14 4 Read mode is entered 5 Data is output to pins D0 through D7 The timing for steps 2 through 5 above is shown in Figure 15 6 Figure 15 6 PROM Read Timing Address Input A0 A14 CE Input OE Input D0 D7 Hi Z...

Page 237: ...ontents by light and to prevent internal circuits from mulfunction due to light coming in through the erasure window mask the window with opaque film after writing the EPROM 15 5 Screening of One Time PROM Versions One time PROM versions µPD78P083CU 78P083GB 3B4 78P083GB 3 MTX cannot be fully tested by NEC before shipment due to the structure of one time PROM Therefore after users have written dat...

Page 238: ...APTER 16 INSTRUCTION SET This chapter describes each instruction set of the µPD78083 subseries as list table For details of its operation and operation code refer to the separate document 78K 0 series USER S MANUAL Instruction IEU 1372 ...

Page 239: ...unction names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 16 1 Operand Identifiers and Description Methods Identifier Description Method r X R0 A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp AX RP0 BC RP1 DE RP2 HL RP3 sfr Special function register symbolNote sfrp Special function register symbol 16 bit manipulatable register even addre...

Page 240: ...arry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses H L Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit dat...

Page 241: ...A HL byte HL byte A 2 8 9 HL byte A A HL B 1 6 7 A HL B HL B A 1 6 7 HL B A A HL C 1 6 7 A HL C HL C A 1 6 7 HL C A A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 A addr16 XCH A DE 1 4 6 A DE A HL 1 4 6 A HL A HL byte 2 8 10 A HL byte A HL B 2 8 10 A HL B A HL C 2 8 10 A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 Wh...

Page 242: ... 2 8 9 A CY A HL byte A HL B 2 8 9 A CY A HL B A HL C 2 8 9 A CY A HL C A byte 2 4 A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr 2 4 5 A CY A saddr CY A addr16 3 8 9 A CY A addr16 CY A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY A HL C 2 8 9 A CY A HL C CY Notes 1 When the internal high speed RA...

Page 243: ...CY A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY A HL C 2 8 9 A CY A HL C CY A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A 2 4 r r A A saddr 2 4 5 A A saddr A addr16 3 8 9 A A addr16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B A HL C 2 8 9 A A HL C Notes 1 When the internal high speed RAM area is acces...

Page 244: ...1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B A HL C 2 8 9 A A HL C A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9 A addr16 A HL 1 4 5 A HL A HL byte 2 8 9 A HL byte A HL B 2 8 9 A HL B A HL C 2 8 9 A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area ex...

Page 245: ... after Addition Decimal Adjust Accumulator after Subtract CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit CY A bit 2 4 CY A bit CY PSW bit 3 7 CY PSW bit CY HL bit 2 6 7 CY HL bit saddr bit CY 3 6 8 saddr bit CY sfr bit CY 3 8 sfr bit CY A bit CY 2 4 A bit CY PSW bit CY 3 8 PSW bit CY HL bit CY 2 6 8 HL bit CY Notes 1 When the internal high speed RAM area is accessed or instruction with ...

Page 246: ...W bit 3 7 CY CY PSW bit CY HL bit 2 6 7 CY CY HL bit saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 SET1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 HL bit 2 6 8 HL bit 1 saddr bit 2 4 6 saddr bit 0 sfr bit 3 8 sfr bit 0 CLR1 A bit 2 4 A bit 0 PSW bit 2 6 PSW bit 0 HL bit 2 6 8 HL bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY Notes 1 When the internal high speed RAM area is accessed...

Page 247: ...P SP 2 SP word 4 10 SP word MOVW SP AX 2 8 SP AX AX SP 2 8 AX SP addr16 3 6 PC addr16 BR addr16 2 6 PC PC 2 jdisp8 AX 2 8 PCH A PCL X BC addr16 2 6 PC PC 2 jdisp8 if CY 1 BNC addr16 2 6 PC PC 2 jdisp8 if CY 0 BZ addr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ addr16 2 6 PC PC 2 jdisp8 if Z 0 Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the...

Page 248: ...bit BTCLR PC PC 3 jdisp8 if A bit 1 then reset A bit PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit PC PC 3 jdisp8 if HL bit 1 then reset HL bit B B 1 then PC PC 2 jdisp8 if B 0 C C 1 then PC PC 2 jdisp8 if C 0 saddr saddr 1 then PC PC 3 jdisp8 if saddr 0 SEL RBn 2 4 RBS1 0 n NOP 1 2 No Operation EI 2 6 IE 1 Enable Interrupt DI 2 6 IE 0 Disable Interrupt HALT 2 6 Set HALT Mode STOP 2 6 Set STOP Mo...

Page 249: ...226 CHAPTER 16 INSTRUCTION SET 16 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ ...

Page 250: ...DD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP r MOV MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP B C DBNZ sfr MOV MOV saddr MOV MOV DBNZ INC ADD DEC ADDC SUB SUBC AND OR XOR CMP addr16 MOV PSW MOV MOV PUSH POP DE MOV HL MOV ROR4 ROL4 HL byte MOV HL B HL C X MU...

Page 251: ...HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand First Operand A bit MOV1 BT SET1 BF CLR1 BTCLR sfr bit MOV1 BT SET1 BF CLR1 BTCLR saddr bit MOV1 BT SET1 BF CLR1 BTCLR PSW bit MOV1 BT SET1 BF CLR1 BTCLR HL bit MOV1 BT SET1 BF CLR1 BTCLR CY MOV1 MOV1 MOV1 MOV1 MOV1 SET1 AND1 AND1 AND1 AND1 AND1 CLR1 OR1 OR1 OR1 OR1 OR1 NOT1 XOR1 XOR1 XOR1 XOR1 XOR1 wor...

Page 252: ...tions branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP EI DI HALT STOP ...

Page 253: ...230 CHAPTER 16 INSTRUCTION SET MEMO ...

Page 254: ...EVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µPD78083 subseries Figure A 1 shows the configuration of the development tools ...

Page 255: ...e Assembler package C compiler package C library source file System simulator Screen debugger or integrated debugger Device file Host machine PC or EWS Interface adapter only when integrated debugger is used PROM writing environments PROM programmer Programmer adapter PROM containing version In circuit emulator Interface adapter only when integrated debugger is used Emulation board Emulation probe...

Page 256: ...µS DF78083 CC78K 0 L This is a function source program configurating object library included in CC78K 0 C compiler C Library Source File Necessary for changing object library included in CC78K 0 in according to customer s specifications Part Number µS CC78K0 L Note The DF78083 can be used commonly with all the RA78K 0 CC78K 0 SM78K0 ID78K0 and SD78K 0 Remark of the part number differs depending on...

Page 257: ...78P083CU 42 pin plastic shrink DIP 600 mil PROM programmer 42 pin ceramic shrink DIP with window 600 mil adapter PA 78P083GB 44 pin plastic QFP 10 10 mm A 2 2 Software PG 1500 controller This program controls the PG 1500 from the host machine through serial and or parallel interface cable s Part Number µS PG1500 Remark of the part number differs depending on the host machine and OS used Refer to t...

Page 258: ...er mode commercially available conversion adapter is necessary IE 78000 R This is in circuit emulator that debugs hardware and software when application system using In circuit emulator 78K 0 series is developed It supports screen debugger SD78K 0 and is used with emulation supporting screen probe This emulator is connected to host machine or PROM programmer for efficient debugger debugging IE 780...

Page 259: ...ftware quality can be improved This simulator is used with optional device file DF78083 Part Number µS SM78K0 Remark of the part number differs depending on the host machine and OS used Refer to the table below µS SM78K0 Host Machine OS Medium AA13 PC 9800 Series MS DOS 3 5 inch 2HD Ver 3 30 to 6 2Note Windows Ver 3 0 to 3 1 AB13 IBM PC AT and their Refer to A 4 3 5 inch 2HC compatible machines Wi...

Page 260: ...tem performance analyzer This program is used in combination with optional device file DF78083 Part Number µS ID78K0 Remark of the part number differs depending on the host machine and OS used Refer to the table below µS ID78K0 Host Machine OS Medium AA13 PC 9800 Series MS DOS 3 5 inch 2HD Ver 3 30 to 6 2Note Windows Ver 3 1 AB13 IBM PC AT and their Refer to A 4 3 5 inch 2HC compatible machines Wi...

Page 261: ...K0 or SD78K 0 Part Number µS DF78083 Note This device file can be used for any of the RA78K 0 CC78K 0 SM78K0 ID78K0 SD78K 0 devices Remark of the part number differs depending on the host machine and OS used Refer to the table below µS SD78K0 µS DF78083 Host Machine OS Medium 5A13 PC 9800 Series MS DOS 3 5 inch 2HD 5A10 Ver 3 30 to 6 2Note 5 inch 2HD 7B13 IBM PC AT and their Refer to A 4 3 5 inch ...

Page 262: ... Development Support System Windows Ver 3 0 to Ver 3 1 is necessary OS Version PC DOS Ver 5 02 to 6 3 J6 1 VNote to J6 3 VNote IBM DOS J5 02 VNote MS DOS Ver 5 0 to 6 22 5 0 VNote to 6 2 VNote Note Only English mode is supported Caution The task swap function is not available with this software through the function is provided in MS DOS version 5 0 or later ...

Page 263: ... R BK 78K I series IE 78130 R IE 78140 R 78K II series IE 78230 RNote IE 78230 R A IE 78240 RNote IE 78240 R A 78K III seires IE 78320 RNote IE 78327 R IE 78330 R IE 78350 R Note Maintenance product Table A 2 System Up Method from Other In Circuit Emulator to IE 78000 R A Series Name In Circuit Emulator Owned Board to be Purchased 75X XL series IE 75000 RNote 1 IE 75001 R IE 78000 R BKNote 2 78K I...

Page 264: ... L K R Q I H P J G EV 9200G 44 G0E ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R 15 0 10 3 10 3 15 0 4 C 3 0 0 8 5 0 12 0 14 7 5 0 12 0 14 7 8 0 7 8 2 0 1 35 0 35 0 1 1 5 0 591 0 406 0 406 0 591 4 C 0 118 0 031 0 197 0 472 0 579 0 197 0 472 0 579 0 315 0 307 0 079 0 053 0 014 0 059 0 004 0 005 φ φ No 1 pin index Based on EV 9200G 44 1 Package drawing in mm ...

Page 265: ...18 0 433 0 433 0 618 0 197 0 197 0 02 0 062 0 087 0 062 0 8 0 02 10 8 0 0 05 0 8 0 02 10 8 0 0 05 φ φ φ 0 002 0 001 0 002 0 002 0 002 0 001 0 002 0 002 0 003 0 004 0 003 0 004 0 001 0 002 φ φ φ 0 001 0 002 0 004 0 005 0 001 0 002 Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimensions for QFP refer to SEMICONDUCTOR ...

Page 266: ...BEDDED SOFTWARE APPENDIX B EMBEDDED SOFTWARE This section describes the embedded software which are provided for the µPD78083 subseries to allow users to develop and maintain the application program for these subseries ...

Page 267: ...experimental production Mass production object Use for mass production S01 Source program Can be purchased only when object for mass production has been purchased Host Machine OS Medium 5A13 PC 9800 Series MS DOS 3 5 inch 2HD 5A10 Ver 3 30 to 6 2Note 5 inch 2HD 7B13 IBM PC AT and their Refer to A 4 3 5 inch 2HC 7B10 compatible machines 5 inch 2HC 3H15 HP9000 series 300 HP UX rel 7 05B Cartridge ta...

Page 268: ...ge data converted by translator Fuzzy Inference Module Part Number µS FI78K0 PC 9800 series IBM PC AT and their compatible machines FD78K0 This software supports evaluating and adjusting fuzzy knowledge data at hardware level by using Fuzzy Inference in circuit emulator Debugger Part Number µS FD78K0 PC 9800 series IBM PC AT and their compatible machines Remark of the part number differs depending...

Page 269: ...246 APPENDIX B EMBEDDED SOFTWARE MEMO ...

Page 270: ...63 E External interrupt mode register INTM0 179 External interrupt mode register INTM1 125 179 I IF0H Interrupt request flag register 0H 175 176 IF0L Interrupt request flag register 0L 175 176 IF1L Interrupt request flag register 1L 175 176 IMS Memory size switching register 206 INTM0 External interrupt mode register 0 175 179 INTM1 External interrupt mode register 1 125 175 179 Interrupt mask fla...

Page 271: ...178 PSW Program status word 33 175 180 PUOH Pull up resistor option register H 66 PUOL Pull up resistor option register L 66 R RXB Receive buffer register 139 S SAR Successive approximation register 121 SFR Special function register 29 37 49 Serial operating mode register 2 CSIM2 140 148 150 163 T TCL0 Timer clock select register 0 113 TCL2 Timer clock select register 2 106 116 TCL5 Timer clock se...

Page 272: ...een changed Figure 7 3 Watchdog Timer Mode Register Format notes and CHAPTER 7 WATCHDOG TIMER cautions have been added Description of 7 4 2 Interval timer operation has been changed Cautions with regard to rewriting TCL0 to other than same data CHAPTER 8 CLOCK OUTPUT CONTROL has been added to 8 3 1 Timer clock select register 0 TCL0 CIRCUIT The HSC bit has been added to the A D Converter Mode CHAP...

Page 273: ...DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following Development Tools have been added IE 78000 R A IE 70000 98 IF B IE 70000 98 N IF IE 70000 PC IF B IE 78000 R SV3 SM78K0 ID78K0 A 4 OS for IBM PC has been added Table A 2 System Up Method from Other In Circuit Emulator to IE 78000 R A has been added B 1 Real time OS has been added APPENDIX B EMBEDDED SOFTWARE ...

Page 274: ...merica NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 889 1689 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Corporation Semiconductor Solution Engineering Division Technical Information Sup...

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