Pull low SCL
Pull low SCL
Pull low SCL
Data Byte
Data Byte
SCL
1
1
0
0 0 0 0 0
A
A
A
SDA
In
SDA
Out
INTO
Write REG#19H to release
Shift register to data buffer
DDC2B=1
ADDR=0
R/W=0
START=0
STOP=1
DDC2B=1
ADDR=0
R/W=0
START=0
STOP=0
DDC2B=1
ADDR=0
R/W=0
START=0
STOP=0
DDC2B=1
ADDR=0
R/W=0
START=1
STOP=0
DDC2B state write timing
Pull low SCL
Pull low SCL
Data Byte
Data Byte
SCL
1
1
0
0 0 0 0
SDA
In
SDA
Out
INTO
Write REG#19H to release
Data buffer to shift reg
1
A
A
N
DDC2B=1
ADDR=0
R/W=1
START=0
STOP=1
DDC2B=1
ADDR=0
R/W=1
START=0
STOP=0
DDC2B=1
ADDR=0
R/W=1
START=1
STOP=0
DDC2B state write timing
55
Summary of Contents for Diamond Scan 51
Page 9: ...6 MultiSync MV521 Diamand Scan 51 ...
Page 71: ...11 Monolithic triple 13 5nS CRT driver 68 ...
Page 72: ...69 ...
Page 73: ...70 ...
Page 74: ...71 ...
Page 103: ...95 SCHEMATIC DIAGRAMS 1 Video Board ...
Page 104: ...96 2 Main Board ...