NEC Electronics (Europe) GmbH
- 7 -
2 Board
description
2.1 Overview
Pin Patch Area
Pin Patch Area
Pi
n Pat
c
h Are
a
Pi
n Pat
c
h Are
a
CN0
CN63
CN2
CN28
CN1
CN6
CN7
CN8
CN1
0
CN5
CN4
CN3
CN1
1
CN1
2
CN1
3
CN1
5
CN1
4
CN31
CN29
CN
3
0
CN
3
2
JP11
JP15
CN49
JP1
CN52
JP2
1
2
JP26
JP27
JP28
JP29
JP7
CN47
CN46
CN45
CN44
2
1
2
1
2
1
2
1
CN53
TP1
TP15
TP
5
0
TP
11
TP
1
2
TP
4
8
TP
5
4
TP
5
6
TP
5
8
TP
6
2
TP
6
0
TP7
TP6
CN18
CN17
CN37
CN20
CN19
CN22
CN21
CN34
CN33
CN36
CN35
JP
1
2
JP1
0
JP1
3
JP
1
6
JP1
4
JP1
7
JP
2
0
JP1
8
JP2
1
JP
2
4
JP2
2
JP2
5
JP
3
6
JP3
3
JP3
7
JP
4
0
JP3
8
JP4
1
CN3
8
CN39
CN
40
CN23
CN
4
8
1
2
2
1
CN
2
4
2
1
CN
9
2
1
JP22
CN1
6
JP3
JP
3
JP5
JP4
JP8
JP6
JP9
TP5
TP4
CN54
CN55
CN56
CN5
9
CN6
0
CN5
7
CN5
8
Figure 2-1
Board overview
Basically the board is divided into two areas, an ‘Electrical Area’ and a ‘Functional Area’.
In Figure 2-1 the Electrical Area is surrounded in by a red line and the Functional Area is surrounded by a blue line.
2.1.1 Electrical
Area
In the center of the Electrical Area a 180 pin SMD pad field is located that any of the F-Series devices can be
assembled to.
On each side of the Device Pad Field a Pin Patch Area is located. In this patch area access is given to
-
each pin of the device
- VDD
- VSS
Further more SMD and through hole components can directly be soldered onto the Pin Patch Area to allow simple
networks to be easily built up.
The circuitry available at each pin inside the Pin Patch Area is described in the figure below:
