Nautel XR6, Troubleshooting Manual, Page: 72 / 291

XR6/XR3 Troubleshooting Manual Detailed Circuit Descriptions
Page 2-4 Issue 3.0 2009-07-15
Cabinet temperature
Low voltage temperature sensor U5 provides a dc voltage (between 0 and 5 V) which represents the
ambient cabinet temperature. This voltage is buffered by operational amplifier U8A and associated
components and applied to ADC U12 for application to the front panel's diagnostic display.
Microcontroller
Microcontroller IC U22 interfaces between the diagnostic display and its associated soft-keys. It
controls the level of the
Carrier Ref signals (see “Carrier reference voltage” on page 2-1 ), which
ultimately determines the forward power level of the transmitter. It also acts as an internal and
external serial interface for transmitter alarm and status signals.
CPLD
Complex programmable logic device (CPLD) U18 continuously reads digital inputs for all transmitter
alarm events. It is programmed to perform root cause detection of a fault as well as high-speed fault
protection. Depending on the nature of the fault, the CPLD generates transmitter
Shutback outputs
(J7-1 and J7-2) or various digital control/inhibit signals via a parallel data bus.
RF synthesizer P WB (NAPE70C)
See electrical schematics Figures SD-12 and SD-13.
Microprocessor
The microprocessor consists of an 87C51 integrated circuit (U4) which is clocked at the system
oscillator frequency (10.0000 MHz). Firmware resides in U4's internal four kilobytes of EPROM
memory. The microprocessor's functions are to generate control information for the DDS circuit,
generate control information for the N divider circuit, and provide control signals to all power
modules during transmitter tuning.
DDS control information
The RF carrier frequency is set using five binary coded decimal (BCD) switches (S1 through S5).
When a current sink to ground is applied at the
Reset DDS input, or during turn on, the
microprocessor monitors these switches and outputs the appropriate 48-bit value to the DDS
frequency tuning word #1 register. The 48-bit value is written in six consecutive bytes to the DDS's
six internal registers. The
WRB/SCLK signal is enabled on each write cycle.