Xltek EMU128 Headbox
User & Service Manual
21
Digital Motherboard
(Schematic diagram SD-102194 Rev D3)
J7 is the connector for plugging in the cable to the computer. U1 converts the +12V to
+5V for powering the rest of the chips on this board. VPW1 and VPW2 are the two wires
of a 12VAC 40KHz power source on the XLTEK Headbox Interface Card in the
computer. The high frequency allows the use of miniature ferrite transformers in the
headbox. The letter D in a triangle is the ground return for the +12V and the ground
reference for the differential communication pairs, which are the rest of the signals on
J7. SATX
±
is the pair for the TX UART in the computer, transmitting commands to the
headbox at 19.53Kbaud, 1 start bit, 9 data bits, 1 stop bit. SARX
±
is for the replies. A
failure of these signals at U4 or U13 results in the message “Please connect a headbox
before starting study.” A command or reply failure on an individual Digital PCB results in
the message, “Attempt to send command to unconnected board.” The other three pairs
are used for the digitized waveforms, sent in synchronous serial format with serial clock
frequency of 5 MHz. SSCK
±
=Clock, SSDAT
±
=Data, SSFS
±
=Frame Sync. The Frame
Sync pulse is one clock period duration and shows where a word begins.
The chips are differential drivers and receivers. A driver converts a digital logic level to
voltages more suitable for transmission along the cable. Conversely a receiver converts
the balanced differential voltage on the cable to a digital logic signal. Receiver U13
processes SATX
±
and applies the logic level to drivers U14 and U15 for generating
individual differential drives to the four Digital PCBs. Diode D2 is for protection only.
R17 terminates the twisted pair in its characteristic impedance. Drivers U3-U6 operate
on signals SCK, SFS, SDAT, and SARX. Driver U2 is not populated on the board.
Because the latter signals come from the open-collector outputs of optocouplers on the
four Digital PCBs, they are combined when they are connected together. In this product
the pull-up resistors for these signals are left off the individual Digital PCBs and are
shown instead on this assembly as R18-R21.
Relay Matrix Board
(Schematic diagram SD-102910E)
EEG signals enter the headbox through J6. For example, in normal operation the first
channel relays, K1 and K33, are de-energized. The signal flows from K1-5 to K1-1
(sheet 3), then from K33-4 to K33-1 (sheet 4), then through R1 to J4-31 (sheet 2) where
it continues to the Analog PCB. To apply a stimulus voltage, K1 or K33 must be
energized to connect the patient electrode to the STIM+ input (J1-2 on sheet 2), or the
STIM- input, respectively. The voltage travels through the Normally Open contact. Under
these conditions, the EEG signal path is through R34 or R66 instead of the Normally
Closed relay contact. The resistance is such as to still give accurate signal acquisition
while protecting the amplifier from the stimulus voltage. Back-to-back zener diodes D2
and D3 keep the stim voltage from exceeding 200V, which could harm the headbox.
The relay coils are driven directly from shift register U65-U72 outputs. On command
from the computer, the Digital PCB transmits the new setting to the shift registers.
SCDAT is the data, SCSTB is the clock, and nLEDEN latches the new setting. Network