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Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
It is recommended to perform the following steps to enter low-power state and wake up:
1.
Wait for the transmission of the current frame to complete, then reset ETH_DMAOPMOD.ST to turn off
TxDMA;
2.
Clear ETH_MACCFG.TE and ETH_MACCFG.RE, close MAC transmit engine and MAC receive engine;
3.
By reading ETH_DMASTS.RI, make sure to wait for RxDMA to read all frames in RxFIFO before closing
RxDMA;
4.
Configure and enable external interrupt line 19 to generate events or interrupts. If external interrupt line 19 is
configured to generate an interrupt, also need to write the interrupt handler ETH_WKUP_IRQHandler, and clear
the interrupt flag bit of external interrupt line 19 in interrupt handler;
5.
Set ETH_MACPMTCTRLSTS.MGKPKTEN to 1 to enable detection of Magic Packet wakeup frames or set
ETH_MACPMTCTRLSTS.RWKPKTEN to 1 to enable detection of remote wakeup frames;
6.
Set ETH_MACPMTCTRLSTS.PWRDWN to 1 to enable low-power consumption mode;
7.
Set ETH_MACCFG.RE to 1, open MAC receive engine;
8.
Configure MCU to enter the relevant low-power mode;
9.
After received a valid wake-up frame, Ethernet module exits low-power state;
10.
Read ETH_MACPMTCTRLSTS register to clear power management event flag, turn on MAC transmit engine,
and TxDMA and RxDMA;
11.
Set system clock, enable HSE and configure RCC clock parameters to restore system to normal state.
25.4.8
Ethernet DMA function description
The dedicated DMA controller of Ethernet module can realize the frame data transmission between FIFO and system
storage, reducing the intervention of CPU. The communication between DMA and CPU is achieved through 2 data
structures:
Descriptor list (chain or ring) and data buffer
Control and Status register
The application needs to allocate a list of storage descriptors and physical memory for data caching. Contains two
descriptor queues for transmitting and receiving respectively, and the descriptors are stored in the memory in the
form of pointers to the buffer. The base address of the transmit descriptor queue is stored in ETH_DMATXDLADDR
register, and the transmit descriptor is composed of four descriptor words TDES0-TDES3; the base address of the
receive descriptor queue is stored in ETH_DMARXDLADDR register, and the receive descriptor is composed of
four descriptor words RDES0-RDES3. Each descriptor can point to up to 2 buffers for storing frame data.
The data buffer allows to store the entire or partial data of the same frame, but not more than one frame. Descriptor
queues can be forward-connected through an explicit chain structure or an implicit ring structure. Set RDES1.RCH
of the receive descriptor and TDES1.TCH of the transmit descriptor to 1, which can realize the explicit connection
of the descriptor (the chain structure of the descriptor), and the buffer address will be stored in RDES2 and TDES2.
The address where the next descriptor is stored. Set RDES1.RCH of the receive descriptor and TDES1.TCH of the
transmit descriptor to 0, which can realize the implicit connection of the descriptor (the ring structure of the
