710
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Figure 25-4 MII interface signal line
MII_Tx_EN: Transmit enable signal, this signal must appear synchronously with the start bit of the data
preamble, and keep it until the transmission is completed.
MII_Tx_CLK: The continuous clock signal used for transmit data. When the data transmission rate is 10Mbps,
the clock is 2.5MHz; when the data transmission rate is 100Mbps, the clock is 25MHz.
MII_TxD[3:0]: Transmit data line, transmit 4-bit data each time, the data is only valid when the MII_Tx_EN
signal is enabled. MII_TxD[0] is the lowest bit of the data and MII_TxD[3] is the highest bit. When the
MII_Tx_EN signal is disabled, the data transmitted by the PHY is invalid.
MII_Rx_DV: Receive data valid signal, controlled by PHY, signal valid means PHY has prepared data for MAC
to receive. This signal must appear synchronously with the first 4 bits of the frame data and remains active until
the data transfer is complete. This signal must be deasserted before the first clock occurs after the last 4 bits of
data have been transferred. In order to ensure that the received data is normal, the active level cannot appear
after the SFD on the data line appears.
MII_Rx_ER: Receive error signal, keep the valid state for at least one MII_Rx_CLK clock cycle, indicating that
the MAC detects an error in reception. The cause of the error needs to be analyzed according to the state of
MII_Rx_DV and the value of MII_RxD[3:0]. Please refer to Table 25-4 for the code of the receiving interface
signal.
MII_Rx_CLK: The clock signal used to receive data. When the data transmission rate is 10Mbps, the clock is
2.5MHz; when the data transmission rate is 100Mbps, the clock is 25MHz.
MII_RxD[3:0]: Receive data line, receive 4-bit data each time, the data is valid when the MII_Rx_DV signal is
valid. MII_RxD[0] is the lowest bit of the data and MII_RxD[3] is the highest bit. If MII_Rx_DV is invalid, but
MII_Rx_ER is valid, MII_RxD[3:0] data value has specific meaning, please refer to Table 25-4 for details.
MII_CRS: Carrier sense signal, controlled by PHY, only works in half-duplex mode. This signal is enabled when
the transmitting or receiving medium is not idle. PHY must ensure that the MII_CRS signal remains valid for
the entire duration of the collision. This signal does not need to be synchronized with the transmit/receive clock.
MAC controller
PHY
MII_Tx_EN
MII_Tx_CLK
MII_TxD[3.0]
MII_Rx_DV
MII_Rx_ER
MII_Rx_CLK
MII_RxD[3:0]
MII_CRS
MII_COL
