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Nations Technologies Inc.

Tel

：

+86-755-86309900

：

[email protected]

Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China

recommended to enable the SPI module before the host sends the clock).

In some configurations, when the last data is sent, the BUSY flag (SPI_STS.BUSY) can be used to wait for the end

of the data sending.

Continuous and discontinuous transmission.

When sending data in master mode, if the software is fast enough to detect each TE (SPI_STS.TE) rising edge (or

TE interrupt), and the data is written to the SPI_DAT register immediately before the end of the ongoing transmission.

At this time, the SPI clock remains continuous between the transmission of data items, and the SPI_STS.BUSY bit

will not be cleared, continuous communication can be achieved.

If the software is not fast enough, it will result in discontinuous communication; in this case, the SPI_STS.BUSY bit

is cleared between the transmission of each data items (see Figure 21-10 below).

In master receive-only mode (SPI_CTRL1.RONLY = 1), communication is always continuous and the BUSY flag

(SPI_STS.BUSY) is always high.

In slave mode, the continuity of communication is determined by the SPI master device. However, even if the

communication is continuous, the BUSY flag (SPI_STS.BUSY) will be low for at least one SPI clock cycle between

each data item (see Figure 21-9).

Figure 21-10 Schematic diagram of TE/BUSY change when BIDIRMODE = 0 and RONLY = 0 are transmitted discontinuously.

21.3.3

Status flag

The SPI_STS register has 3 flag bits to monitor the status of the SPI:

Send buffer empty flag bit (TE)

When the send buffer is empty, the TE flag (SPI_STS.TE) is set to 1, which means that new data can be written into

the SPI_DAT register. When the send buffer is not empty, the hardware will clear this flag to 0.

Receive buffer non-empty flag bit (RNE)

When the receive buffer is not empty, the RNE flag (SPI_STS.RNE) is set to 1, so the user knows that there is data

in the receive buffer. After reading the SPI_DAT register, the hardware will set this flag to 0.

BUSY flag bit (BUSY)

DATA1=0x11

SCK

MOSI

（

out

）

TE flag

Tx buffer

（

write to SPI_DAT

）

Configure

：

CLKPOL=1.CLKPHA=1

0x11

0x22

0x33

Wait until TE=1,write 0x33 into SPI_DAT

Write 0x11 into SPI_DAT

Wait until TE=1,write 0x22 into SPI_DAT

DATA2=0x22

DATA3=0x33

BUSY flag

Wait TX=1

Wait BUSY=0

Summary of Contents for N32G45 Series

Page 1: ...N32G45x series 32 bit ARM Cortex M4 microcontroller User manual V3 0...

Page 2: ...1 EXTI register review 44 2 3 2 EXTI interrupt mask register EXTI_IMASK 44 2 3 3 EXTI event mask register EXTI_EMASK 45 2 3 4 Rising trigger selection register EXTI_RT_CFG 45 2 3 5 Falling trigger se...

Page 3: ...registers 95 5 4 1 BKP register overview 95 5 4 2 Backup Data Register x BKP_DATx x 1 42 97 5 4 3 Backup Control Register BKP_CTRL 97 5 4 4 Backup Control Status Register BKP_CTRLSTS 98 Reset and clo...

Page 4: ...registers 159 7 3 1 GPIO register overview 159 7 3 2 GPIO port low configuration register GPIOx_PL_CFG 160 7 3 3 GPIO port high configuration register GPIOx_PH_CFG 161 7 3 4 GPIO port input data regis...

Page 5: ...gister DMA_INTSTS 195 8 5 3 DMA interrupt flag clear register DMA_INTCLR 195 8 5 4 DMA channel x configuration register DMA_CHCFGx 196 8 5 5 DMA channel x transfer number register DMA_TXNUMx 198 8 5 6...

Page 6: ...229 9 12 3 ADC control register 1 ADC_CTRL1 230 9 12 4 ADC control register 2 ADC_CTRL2 233 9 12 5 ADC sampling time register 1 ADC_SAMPT1 235 9 12 6 ADC sampling time register 2 ADC_ SAMPT2 235 9 12...

Page 7: ...wave 256 10 4 11 Synchronous trigger to generate different triangle waves 256 DAC register 257 10 5 1 DAC registers overview 257 10 5 2 DAC control register DAC_CTRL 257 10 5 3 DAC software trigger re...

Page 8: ...mode control register TIMx_SMCTRL 309 11 4 5 DMA Interrupt enable registers TIMx_DINTEN 312 11 4 6 Status registers TIMx_STS 313 11 4 7 Event generation registers TIMx_EVTGEN 315 11 4 8 Capture compar...

Page 9: ...n x 2 3 4 and 5 363 12 4 1 Register Overview 363 12 4 2 Control register 1 TIMx_CTRL1 365 12 4 3 Control register 2 TIMx_CTRL2 367 12 4 4 Slave mode control register TIMx_SMCTRL 368 12 4 5 DMA Interru...

Page 10: ...block diagram 399 14 2 2 GPIOs of RTC 400 14 2 3 RTC register write protection 400 14 2 4 RTC clock and prescaler 400 14 2 5 RTC calendar 401 14 2 6 Calendar initialization and configuration 401 14 2...

Page 11: ...egister RTC_ OPT 421 CRC calculation unit 423 Introduction 423 Main features 423 15 2 1 CRC32 423 15 2 2 CRC16 423 Function description 424 15 3 1 CRC32 424 15 3 2 CRC16 424 CRC registers 425 15 4 1 C...

Page 12: ...terface SDIO 441 Main features of SDIO 441 SDIO bus topology 442 SDIO function description 444 18 3 1 SDIO adapter 444 18 3 2 SDIO AHB Interface 455 Card function description 456 18 4 1 Confirmation o...

Page 13: ...gister SDIO_FIFOCOUNT 495 18 7 16 SDIO data FIFO register SDIO_DATFIFO 496 Universal serial bus full speed device interface USB_FS_Device 497 Introduction 497 Main features 497 Clock configuration 498...

Page 14: ...5 20 4 6 Message storage 538 20 4 7 Bit time characteristic 539 CAN interrupt 542 20 5 1 Error management 543 20 5 2 Bus Off recovery 543 CAN Configuration Flow 543 CAN Register File 545 20 7 1 Regist...

Page 15: ..._CRCTDAT 604 21 5 9 SPI_ I2 S configuration register SPI_I2SCFG 604 21 5 10 SPI_I2 S prescaler register SPI_I2SPREDIV 606 I2 C interface 607 Introduction 607 Main features 607 Function description 607...

Page 16: ...rt 663 USART registers 663 23 7 1 USART register overview 663 23 7 2 USART Status register USART_STS 664 23 7 3 USART Data register USART_DAT 666 23 7 4 USART Baud rate register USART_BRCF 667 23 7 5...

Page 17: ...SPI DMA Control Register QSPI_DMA_CTRL 695 24 6 22 QSPI DMA Transmit Data Level Register QSPI_DMATDL_CTRL 695 24 6 23 QSPI DMA Receive Data Level Register QSPI_DMARDL_CTRL 695 24 6 24 QSPI Data Regist...

Page 18: ...s 2 high register ETH_MACADDR2HI 761 25 5 19 ETH MAC address 2 low register ETH_MACADDR2LO 762 25 5 20 ETH MAC address 3 high register ETH_MACADDR3HI 762 25 5 21 ETH MAC address 3 low register ETH_MAC...

Page 19: ...rent receive descriptor address register ETH_DMACHRXDESC 788 25 5 53 ETH DMA current transmit buffer address register ETH_DMACHTXBADDR 789 25 5 54 ETH DMA current receive buffer address register ETH_D...

Page 20: ...neral operation process 817 28 3 2 DMA application 818 28 3 3 Image size 818 28 3 4 Image area 818 28 3 5 Image scaling 818 28 3 6 Soft reset 819 28 3 7 Interrupts 819 28 3 8 Read FIFO data 819 28 3 9...

Page 21: ...09 Baoshen Road Hi tech Park North Nanshan District Shenzhen 518057 P R China 29 4 1 DBG register overview 832 29 4 2 ID register DBG_ID 832 29 4 3 Debug control register DBG_CTRL 833 Unique device se...

Page 22: ...s of different I O configurations 137 Table 7 3 Debug port image 145 Table 7 4 ADC1 external trigger injection conversion alternate function remapping 146 Table 7 5 ADC1 external trigger regular conve...

Page 23: ...alternate function remapping 150 Table 7 25 UART5 alternate function remapping 150 Table 7 26 UART6 alternate function remapping 150 Table 7 27 UART7 alternate function remapping 151 Table 7 28 I2C1...

Page 24: ...tchdog channel selection 212 Table 9 3 Right align data 216 Table 9 4 Left aligne data 216 Table 9 5 External trigger for regular channels of ADC1 and ADC2 217 Table 9 6 External trigger for regular c...

Page 25: ...r overview 439 Table 18 1 MMC SD SD I O Card bus pin definition 446 Table 18 2 Command Channel Status Flags 450 Table 18 3 Data Token Format 453 Table 18 4 Transmit FIFO Status Flags 454 Table 18 5 Re...

Page 26: ...W_BUF definitions 501 Table 19 2 How to use double buffering 501 Table 19 3 How to use isochronous double buffering 508 Table 19 4 Resume event detection 509 Table 19 5 USB register overview 511 Table...

Page 27: ...USART register overview 663 Table 24 1 QSPI register overview 681 Table 25 1 ETH module pin configuration alternate 707 Table 25 2 SMI clock configuration range 709 Table 25 3 Transmit interface signa...

Page 28: ...mode configuration 139 Figure 7 4 Alternate function configuration 140 Figure 7 5 High impedance analog mode configuration 141 Figure 8 1 DMA block diagram 184 Figure 8 2 DMA1 request mapping 190 Fig...

Page 29: ...trigonometry generation enable software trigger 252 Figure 11 1 Block diagram of TIM1 and TIM8 267 Figure 11 2 Counter timing diagram with prescaler division change from 1 to 4 268 Figure 11 3 Timing...

Page 30: ...ion in encoder interface mode 300 Figure 11 33 Encoder interface mode example with IC1FP1 polarity inverted 301 Figure 11 34 Example of Hall sensor interface 303 Figure 12 1 Block diagram of TIMx x 2...

Page 31: ...n encoder interface mode 362 Figure 12 28 Encoder interface mode example with IC1FP1 polarity inverted 363 Figure 13 1 Block diagram of TIMx x 6 and 7 386 Figure 13 2 Counter timing diagram with presc...

Page 32: ...dpoint example 503 Figure 19 5 Control transfer 507 Figure 20 1 Topology of CAN network 525 Figure 20 2 CAN working mode 527 Figure 20 3 Dual CAN block diagram 528 Figure 20 4 loopback mode 529 Figure...

Page 33: ...sion CLKPOL 0 587 Figure 21 15 I2S Philips protocol standard waveform 24 bit frame CLKPOL 0 587 Figure 21 16 I2S Philips protocol standard waveform 16 bit extended to 32 bit packet frame CLKPOL 0 588...

Page 34: ...mark 653 Figure 23 14 USART synchronous transmission example 654 Figure 23 15 USART data clock timing example WL 0 654 Figure 23 16 USART data clock timing example WL 1 655 Figure 23 17 RX data sampli...

Page 35: ...gram 791 Figure 26 3 Comparator5 Comparator6 comparator7 connection diagram 792 Figure 27 1 Block diagram of OPAMP1 and OPAMP2 connection diagram 805 Figure 27 2 Block diagram of OPAMP3 and OPAMP4 con...

Page 36: ...ct on this bit read clear rc_w0 Software can read this bit or clear it by writing 0 and writing 1 has no effect on this bit read clear by read rc_r Software can read this bit Reading this bit will aut...

Page 37: ...egister The system tick calibration value is fixed at 18000 When the system tick clock is set to 18 MHz the maximum value of HCLK 8 a 1ms time reference is generated 2 1 2 Interrupt and exception vect...

Page 38: ...obal interrupt 0x0000_0074 14 21 Settable DMA1 channel 4 DMA1 channel 4 global interrupt 0x0000_0078 15 22 Settable DMA1 channel 5 DMA1 channel 5 global interrupt 0x0000_007C 16 23 Settable DMA1 chann...

Page 39: ...7 Settable TIM5 TIM5 global interrupt 0x0000_0108 51 58 Settable SPI3_I2S3 SPI3 I2S3 global interrupt 0x0000_010C 52 59 Settable UART4 UART4 global interrupt 0x0000_0110 53 60 Settable UART5 UART5 glo...

Page 40: ...5 COMP6 global interrupt 0x0000_018C 84 91 Settable COMP7 COMP7 global interrupt 0x0000_0190 85 92 Settable R SRAM R SRAM error interrupt 0x0000_0194 External interrupt event controller EXTI 2 2 1 Int...

Page 41: ...will be generated and the corresponding Pending bit will be set to 1 Writing 1 in the corresponding bit of the Pending register will clear the interrupt request To generate an event the corresponding...

Page 42: ...that control the NVIC interrupt channel mapped to the External Interrupt Controller so that an interrupt coming from one of the 21 lines can be correctly acknowledged Hardware configuration select and...

Page 43: ...l EXTI2_CFG 3 0 Control EXTI3_CFG 3 0 Control EXTI4_CFG 3 0 Control EXTI5_CFG 3 0 Control EXTI6_CFG 3 0 Control EXTI7_CFG 3 0 Control AFIO_EXTI_CFG1 Register AFIO_EXTI_CFG2 Register EXTI0 EXTI1 EXTI2...

Page 44: ...FG Reserved RT_CFG 20 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00Ch EXTI_FT_CFG Reserved FT_CFG 20 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 010h EXTI_SWIE Reserved SWIE 2...

Page 45: ...nt mask on line x 0 Event request from line x is masked 1 Event request from line x is not masked 2 3 4 Rising trigger selection register EXTI_RT_CFG Address offset 0x08 Reset value 0x0000 0000 Bit fi...

Page 46: ...it field Name Description 31 21 Reserved Reserved the reset value must be maintained 20 0 SWIEx Software interrupt on line x When this bit is 0 writing 1 will set the corresponding Pending bit in EXTI...

Page 47: ...etection to clear this bit 2 3 8 EXTI timestamp trigger source selection register EXTI_TS_SEL Address offset 0x18 Reset value 0x0000 0000 Bit field Name Description 31 4 Reserved Reserved the reset va...

Page 48: ...ax 144MHz AHB Bus Matrix Max 144MHz DMA1 EFC Flash DCode DMA TPIU SW JTAG NVIC FPU DSP SBus ICode DMA2 DMA ETH iCache SRAM R SRAM SAC QSPI SDIO RCC CRC APB2 Max 72MHz AFIO APB1 Max 36MHz EXTI GPIOA GP...

Page 49: ...HB2APB2 Among them APB1 contains 26 low speed APB peripherals and the maximum speed of PCLK1 is 36MHz APB2 contains 18 high speed APB peripherals and the maximum speed of PCLK2 is equal to 72MHz 3 1 2...

Page 50: ...004_0000 0xE004_0FFF COMP OPAMP Reserved TIM7 TIM6 TIM5 TIM4 TIM3 TIM2 0x4000_2400 0x4000_27FF 0x4000_2000 0x4000_23FF 0x4000_1800 0x4000_1BFF 0x4000_1400 0x4000_17FF 0x4000_1000 0x4000_13FF 0x4000_0C...

Page 51: ...ding 3 1 3 Boot management Boot address When the system starts the boot mode after reset can be selected through BOOT1 and BOOT0 pins After system reset or exit from standby mode the value of BOOT pin...

Page 52: ...08000000 0x0000_0000 0x1FFF_0000 0x1000_0000 0x2000_0000 1 1 SRAM start 0x08000000 0x1FFF_0000 0x0000_0000 0x1000_0000 0x2000_0000 Embedded boot loader Embedded boot loader program is stored in the sy...

Page 53: ...Page 2 0x0800_1000 0x0800_17FF 2KB Page 255 0x0807_F800 0x0807_FFFF 2KB Information area System memory area 0x1FFF_0000 0x1FFF_3FFF 16KB System configuration area 0x1FFF_F000 0x1FFF_F7FF 2KB Option b...

Page 54: ...HCLK 32MHz the minimum number of waiting periods is 0 When 32MHz HCLK 64MHz the minimum number of waiting periods is 1 When 64MHz HCLK 96MHz the minimum number of waiting periods is 2 When 96MHz HCLK...

Page 55: ...flash programming Main memory programming process Check the FLASH_ STS BUSY bit to confirm that there are no other flash operations in progress Set the FLASH_CTRL PG bit to 1 Write the word to be prog...

Page 56: ...function can be configured to be enabled or disabled through the register and it is enabled by default Option byte Option byte block is mainly used to configure read write protection boot mode configu...

Page 57: ...te 15 8 Corresponding complement code 7 0 Option byte 0x1FFF_F800 nUSER USER nRDP1 RDP1 0x1FFF_F804 nData1 Data1 nData0 Data0 0x1FFF_F808 nWRP1 WRP1 nWRP0 WRP0 0x1FFF_F80C nWRP3 WRP3 nWRP2 WRP2 0x1FFF...

Page 58: ...uration A system reset is required for the configured value to be reloaded to take effect If an attempt is made to program or erase a protected page a protection error flag will be returned in the FLA...

Page 59: ...protected option byte is rewritten to the unprotected L0 level all the main storage areas will be automatically erased and the process is as follows Erasing the option byte block will not result in au...

Page 60: ...Erase Flash main memory area mass erase Allow Allow Allow Allow Flash option byte area Read Write Erase Read Write Erase Read Write Erase Read Write Erase Flash system memory area prohibit prohibit Re...

Page 61: ...and write Read and write Read and write protect level Boot mode SRAM Changing a Protection Level Perform user Access to areas JTAG SWD Main Flash System Memory SRAM L0 level Before 4KB of flash main m...

Page 62: ...e erase Read write erase Read write erase Flash system memory area Prohibit Prohibit Prohibit Prohibit SRAM All Read and write Read and write Read and write Read and write L2 level Before 4KB of flash...

Page 63: ...h main memory area Prohibit Read only Read only Read only L0 or L2 is allowed When changed to L0 the main memory area is automatically erased After 4KB of flash main memory area Prohibit Read write er...

Page 64: ...updated Accordingly it is equivalent to storing only the jump header of the program in the Cache The main features of the instruction buffer are as follows 8KB iCache Support connection mode 4WAY Soft...

Page 65: ...peatedly used codes in iCache to improve the efficiency of code execution iCache module has four latch channels and the size of each channel is 1 4 of the whole cache When using a single channel you m...

Page 66: ...0000 0x2002 3FFF R SRAM supports read and write access of bytes half words and words and supports access to SBus DMA1 DMA2 and ETH Because the bus address of R SRAM is continuously connected to SRAM...

Page 67: ...R BUSY Reset Value 0 0 0 0 0 0 0 0 010h FLASH_CTRL Reserved ECCERRITE EOPITE FERRITE ERRITE OPTWE SMPSEL LOCK START OPTER OPTPG Reserved MER PER PG Reset Value 0 0 0 0 0 0 1 0 0 0 0 0 0 014h FLASH_ADD...

Page 68: ...of the prefetch buffer 0 The prefetch buffer is closed 1 The prefetch buffer is open 4 PRFTBFE Prefetch buffer enable 0 Close the prefetch buffer 1 Enable prefetch buffer 3 Reserved Reserved the rese...

Page 69: ...5 2 4 The FLASH status register FLASH_STS Address offset 0x0C Reset value 0x0000 0000 Bit field Name Description 31 8 Reserved Reserved the reset value must be maintained 7 ECCERR ECC error Read FLAS...

Page 70: ...ved the reset value must be maintained 0 BUSY Busy This bit indicates that a flash operation is in progress At the beginning of flash operation this bit is set to 1 This bit is cleared to 0 when the o...

Page 71: ...set 1 SMP2 mode Before programming it will not judge whether the content of the address where the programming is located has been erased and the Flash will directly start programming If the programmi...

Page 72: ...lect the page to be erased when page erasing Note When the FLASH_STS BUSY bit is 1 this register cannot be written 3 2 5 2 7 Option byte register FLASH_OB Address offset 0x1C Reset value 0x03FF FFFC B...

Page 73: ...only 2 WDG_SW Set watchdog 0 hardware watchdog 1 Software watchdog Note This bit is read only 1 RDPRT1 Read protection L1 level protection 0 Read protection L1 level is not enabled 1 read protection L...

Page 74: ...it Flash address the corresponding lower 6 bit ECC value 3 2 5 2 10 RDN register FLASH_RDN Address offset 0x2C Reset value 0x0000 0000 Bit field Name Description 31 25 Reserved Reserved the reset valu...

Page 75: ...6309900 Email info nationstech com Address Nations Tower 109 Baoshen Road Hi tech Park North Nanshan District Shenzhen 518057 P R China Bit field Name Description Chapter 0 disable 1 enable 3 0 LOCKST...

Page 76: ...range is 1 8V 3 6V mainly used for clock and reset system most analog peripherals powered BKR and MR are internal voltage regulators that can provide power for the digital module power supply system V...

Page 77: ...diode between this supply and the VBAT pin If there is no external battery in the application It is recommended to connect the VBAT pin to VDD with a 100nF ceramic capacitor In RUN SLEEP STOP0 mode th...

Page 78: ...ip Can work with a minimum voltage of 1 8V No external reset circuit is required When VDD or VDDA is lower than the specified threshold VPOR PDR the chip will remain in reset state For more informatio...

Page 79: ...hold This event is internally connected to the interrupt line 16 of the external interrupt which will generate an interrupt if enabled in the external interrupt register Depending on the rising fallin...

Page 80: ...ower modes Mode Condition Enter Exit RUN CPU boot Peripheral configuration Power on system reset low power wake up Enter sleep STOP0 STOP2 standby and VBAT modes SLEEP CPU goes to sleep mode and the k...

Page 81: ...ed off LSE LSI configurable GPIO is maintained and peripheral IO multiplexing is not maintained 16KB R SRAM data retention other SRAM and register data are lost 84B BK register retention GPIOs and EXT...

Page 82: ...e stopped position and the peripherals need to be re initialized at this time The running enable conditions of different modules in different power consumption modes are shown in the following table T...

Page 83: ...a Peripheral Run Sleep Stop 0 Stop 2 Standby VBAT Wakeup capability Wakeup capability Wakeup capability LSI O O O O O O LSE O O O O O O CSS O O RTC Auto wakeup O O O O O O O O O Number of RTC Tamper p...

Page 84: ...power mode 4 FLASH is in sleep Flash itself mode 4 2 1 SLEEP mode The CPU stops and all peripherals including peripherals around the Cortex M4F core such as NVIC SysTick etc can run and wake up the C...

Page 85: ...combined with peripheral clock control mechanism The voltage regulator can be configured in normal or low power mode In STOP0 mode most of the clock sources in the core domain are disabled such as PLL...

Page 86: ...igital logic areas are powered off The main voltage regulator MR is turned off and the HSE HSI PLL is turned off CPU register retention LSE LSI configurable GPIO retention peripheral IO multiplexing i...

Page 87: ...32 768kHz crystal oscillator LSE OSC optional It can be turned on by RCC_BDCTRL LSEEN bit R SRAM data retention which can be turned on by register PWR_CTRL2 SR2STBRET Exit STANDBY mode MCU exits STAN...

Page 88: ...and STANDBY modes To do this two of the three optional RTC clock sources can be selected by software programming RCC_BDCTRL RTCSEL 1 0 as follows 32 768kHz external crystal clock LSE OSC This clock s...

Page 89: ...0 4 4 2 Power control register PWR_CTRL Address offset 0x00 Reset value 0x0000 0700 reset by wakeup from STANDBY mode Bit field Name Description 31 10 Reserved Reserved the reset value must be mainta...

Page 90: ...age thresholds see the description of the MSB bit NOTE See the Electrical Characteristics section in the datasheet for detailed descriptions 4 PVDEN Power supply voltage monitor PVD enabled 0 Disable...

Page 91: ...1 The device is already in VBAT mode 2 PVDO PVD output This bit is only valid when PVD is enabled by the PWR_CTRL PVDEN bit 0 VDD VDDA is higher than the PVD threshold selected by PWR_CTRL PRS 2 0 1 V...

Page 92: ...ndent watchdog wakeup enable 0 Independent watchdog wakeup disable 1 Independent watchdog wake up enable 8 4 LSITRIM 4 0 LSI correction value 3 TMPWPEN TAMPER wake up enable 0 Disable 1 Enable 2 SR2ST...

Page 93: ...86 755 86309900 Email info nationstech com Address Nations Tower 109 Baoshen Road Hi tech Park North Nanshan District Shenzhen 518057 P R China Bit field Name Description 0 EXMODE Extended mode contro...

Page 94: ...upt or event BKP_CTRLSTS Function description Power down backup Tamper detection An tamper detection event clears all backup data register contents The detection function of the TAMPER pin can be enab...

Page 95: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 010h BKP_DAT4 Reserved DAT 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 014h BKP_DAT5 Reserved DAT 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 018h BKP_DAT6 Res...

Page 96: ...P_DAT20 Reserved DAT 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 068h BKP_DAT21 Reserved DAT 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 06Ch BKP_DAT22 Reserved DAT 15 0 Reset Value 0 0 0 0...

Page 97: ...0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0B4h BKP_DAT40 Reserved DAT 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0B8h BKP_DAT41 Reserved DAT 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 98: ...15 10 Reserved Reserved the reset value must be maintained 9 TINTF Tamper interrupt flag This bit is set by hardware when an tamper event is detected and the TPINT_EN bit is 1 This flag is cleared by...

Page 99: ...s reset only after system reset or wake up from standby mode 1 CLRTINT Clear Tamper Detection Interrupt This bit can only be written and the read value is 0 0 invalid 1 Clear the tamper detection inte...

Page 100: ...the figure will finally act on the NRST pin and remain low during the reset process The reset entry vector is fixed at address 0x0000_0004 For more details see Table 2 1 vector table 6 1 2 System res...

Page 101: ...reset instead of entering STANDBY mode Generate low power management reset when entering STOP0 STOP2 mode This reset is enabled by setting the nRST_STOP bit in the user option byte At this time even i...

Page 102: ...o drive RTC RTCCLK Each clock source can be turned on or off independently when it is not used to optimize power consumption Several prescalers can be used to configure the frequencies of the AHB the...

Page 103: ...LASH_CLK to Flash programming USB_CLK to USB interface I2S3CLK I2S2CLK TRNG_CLK 1M ADC1 2 3 4_CLK 1M ADC1 2 3 4_CLK FCLK CPU AHB BUS HCLK SysTick SAC_CLK CRC_CLK APB1 Prescaler 1 2 4 8 16 36MHz MAX PC...

Page 104: ...configuration is shown in See Figure 6 3 For more details please refer to the electrical characteristics section of the datasheet The RCC_CTRL HSERDF bit indicates whether the high speed external osc...

Page 105: ...ks to provide the 48MHz USBCLK clock 6 2 5 LSE clock The LSE crystal is a 32 768KHz low speed external crystal or ceramic resonator It provides a low power and accurate clock source for the real time...

Page 106: ...urce is ready either after a delay to start the stabilization phase or PLL stabilization When the selected clock source is not ready the switching of the system clock will not occur until the target c...

Page 107: ...s divided by 128 as the RTC clock If the VDD power supply is cut off or the internal voltage regulator is turned off the power supply in the 1 8V domain is cut off the RTC state is indeterminate The P...

Page 108: ...I2C1RST UART5RST UART4RST USART3RST USART2RST Reserved SPI3RST SPI2RST Reserved WWDGRST Reserved TIM7RST TIM6RST TIM5RST TIM4RST TIM3RST TIM2RST Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 109: ...red by software When entering the stop0 stop2 standby mode it is cleared by hardware This bit cannot be cleared when PLL is used as the system clock When the HSI HSE is used as the clock source for th...

Page 110: ...nal value for calibrating the frequency of the internal HSI RC oscillator The trimming step is around 40 kHz between two consecutive HSICAL steps and the default value is 16 which can adjust the HSI t...

Page 111: ...CT 3 0 26 24 MCO 2 0 Microcontroller clock output selection Set and cleared by software 0xx no clock output 100 Select system clock SYSCLK output 101 select internal high speed clock HSI output 110 se...

Page 112: ...010 PLL input clock 19 10011 PLL input clock 20 10100 PLL input clock 21 10101 PLL input clock 22 10110 PLL input clock 23 10111 PLL input clock 24 11000 PLL input clock 25 11001 PLL input clock 26 11...

Page 113: ...by 16 7 4 AHBPRES 3 0 AHB prescaler Set and cleared by software to configure the division factor of the AHB clock HCLK 0xxx SYSCLK not divided 1000 SYSCLK divided by 2 1001 SYSCLK divided by 4 1010 S...

Page 114: ...interrupt clear Set by the software to clear the PLLRDIF flag 0 No effect 1 Clear the PLLRDIF flag 19 HSERDICLR HSE ready interrupt clear Set by the software to clear the HSERDIF flag 0 Not used 1 Cle...

Page 115: ...0 No clock security system interrupt caused by HSE clock failure 1 Clock security system interrupt caused by HSE clock failure 6 5 Reserved Reserved the reset value must be maintained 4 PLLRDIF PLL re...

Page 116: ...eripheral Reset Register RCC_APB2PRST Address offset 0x0c Reset value 0x0000 0000 Bit Field Name Description 31 21 Reserved Reserved the reset value must be maintained 20 I2C4RST I2C4 reset Set and cl...

Page 117: ...M1 timer 10 9 Reserved Reserved the reset value must be maintained 8 IOPGRST GPIO port G reset Set or cleared by software 0 Clear the reset 1 Reset GPIO port G 7 IOPFRST GPIO port F reset Set or clear...

Page 118: ...reset 1 Reset the DAC interface 28 PWRRST Power interface reset Set and cleared by software 0 Clear the reset 1 Reset the power interface 27 BKPRST Backup interface reset Set or cleared by software 0...

Page 119: ...et UART5 19 UART4RST UART4 reset Set and cleared by software 0 Clear the reset 1 Reset UART4 18 USART3RST USART3 reset Set or cleared by software 0 clear the reset 1 Reset USART3 17 USART2RST USART2 r...

Page 120: ...are 0 Clear the reset 1 Reset TIM4 timer 1 TIM3RST TIM3 timer reset Set and cleared by software 0 Clear the reset 1 Reset TIM3 timer 0 TIM2RST TIM2 timer reset Set and cleared by software 0 Clear the...

Page 121: ...1 ADC2 clock enabled 12 ADC1EN ADC1 clock enable Set and cleared by software 0 ADC1 clock disabled 1 ADC1 clock enabled 11 SACEN SAC clock enable Set and cleared by software 0 SAC clock disabled 1 SA...

Page 122: ...oftware 0 DMA2 clock disabled 1 DMA2 clock enabled 0 DMA1EN DMA1 clock enable Set and cleared by software 0 DMA1 clock disabled 1 DMA1 clock enabled 6 3 8 APB2 Peripheral Clock Enable Register RCC_APB...

Page 123: ...timer clock enabled 12 SPI1EN SPI1 clock enable Set and cleared by software 0 SPI1 clock disabled 1 SPI1 clock enabled 11 TIM1EN TIM1 timer clock enable Set and cleared by software 0 TIM1 timer clock...

Page 124: ...t value must be maintained 0 AFIOEN Alternate function IO clock enable Set and cleared by software 0 Alternate Function IO clock disabled 1 Alternate Function IO clock enabled 6 3 9 APB1 Peripheral Cl...

Page 125: ...be maintained 23 USBEN USB clock enable Set and cleared by software 0 USB clock disabled 1 USB clock enabled 22 I2C2EN I2C2 clock enable Set and cleared by software 0 I2C2 clock disabled 1 I2C2 clock...

Page 126: ...0 8 Reserved Reserved the reset value must be maintained 7 COMPFILTEN COMP Filter clock enable Set and cleared by software 0 COMP Filter clock disabled 1 COMP Filter clock enabled 6 COMPEN COMP clock...

Page 127: ...d by software 0 Disable RTC clock 1 Enable RTC clock 14 10 Reserved Reserved the reset value must be maintained 9 8 RTCSEL 1 0 RTC clock source selection Set by software to select RTC clock source Onc...

Page 128: ...the PWR_CTRL DBKP bit is set These bits can only be cleared by a backup domain reset Any internal or external reset will not affect these bits 6 3 11 Clock Control Status Register RCC_CTRLSTS Address...

Page 129: ...by software by writing to the RMRSTF bit 0 No MMU reset occurred 1 MMU reset occurred 24 RMRSTF Clear the reset flag Set by the software to clear the reset flag 0 No effect 1 Clear the reset flag 23 R...

Page 130: ...40 KHz oscillator clock cycles 0 Internal 40KHz RC oscillator clock not ready 1 Internal 40KHz RC oscillator clock ready 0 LSIEN Internal low speed oscillator enable Set and cleared by software 0 Dis...

Page 131: ...cleared by software 0 Clear the reset 1 Reset SAC 10 Reserved Reserved the reset value must be maintained 9 RNGCRST RNGC reset Set and cleared by software 0 Clear the reset 1 Reset RNGC 8 0 Reserved...

Page 132: ...DC 1M clock source divided by 31 11111 ADC 1M clock source divided by 32 Note ADC clock must be configured to 1M 10 ADC1MSEL ADC 1M clock source selection Set or cleared by software 0 Select HSI oscil...

Page 133: ...Register 3 RCC_CFG3 Address offset 0x30 Reset value 0x0000 3800 Bit Field Name Description 31 19 Reserved Reserved the reset value must be maintained 18 TRNG1MEN TRNG analog interface clock enable Set...

Page 134: ...rk North Nanshan District Shenzhen 518057 P R China Bit Field Name Description 1111x TRNG 1M clock source divided by 32 10 7 Reserved Reserved the reset value must be maintained 6 BORRSTEN BOR reset e...

Page 135: ...re pins which can be configured by users according to requirements Each GPIO pin can be independently configured as an output input or alternate peripheral function port Except for the analog function...

Page 136: ...PIOx_POD x A B C D E F G The I O configurations in different operation modes are shown in the following table Table 7 1 I O mode and configuration relationship Configuration mode PCFG1 PCFG0 PMODE1 PM...

Page 137: ...According to peripheral function configuration Open drain mode Disable Configurable GPIO outputs 0 when the data is 0 and high impedance when he data is 1 Disable Configurable GPIO outputs 0 when the...

Page 138: ...vel 1 port on the output register make the pin in a high impedance state P MOS is never activated Push pull mode 0 on the output register activates N MOS and the pin outputs low level 1 on the output...

Page 139: ...nate function mode Schmidt trigger input is activated Weak pull up and pull down resistors are disabled In the open drain or push pull configuration the output buffer is turned on Signals of built in...

Page 140: ...057 P R China Figure 7 4 Alternate function configuration Analog mode When the I O port is configured in analog mode Weak pull up and pull down resistors are disabled Read access to the input data reg...

Page 141: ...OSC_OUT has no GPIO function by default BOOT0 pin default configuration is input pull down NRST pull up input and output After the reset the default state of the pin associated with the debug system i...

Page 142: ...set The bit written with 1 is set or cleared accordingly and the bit not written with 1 will not be changed The software does not need to disable interrupts and is completed in a single APB2 write ope...

Page 143: ...disconnected from its original pin and remapped to the new pin Functional remapping of backup domain pins PC13 PC15 7 2 5 3 1 Functional description of backup power domain pins PC13 PC15 PC13 PC15 pin...

Page 144: ...ing RTC calibration clock RTC alarm clock pulse or second pulse When this pin is not used for intrusion detection it can be used to output RTC calibration clock RTC alarm clock pulse or second pulse s...

Page 145: ...n and above packages PD0 and PD1 pins are available and OSC_IN and OSC_OUT are available so there is no need to remap PD0 PD1 to OSC_IN OSC_OUT JTAG SWD alternate function remapping The SWD JTAG debug...

Page 146: ...ternate function remapping The external trigger source of injection conversion and regular conversion of ADC supports remapping See alternate remapping and debug I O configuration register AFIO_RMP_CF...

Page 147: ...ADC4 external trigger injection conversion ADC4 external trigger injection conversion is connected to EXTI14 ADC4 external trigger injection conversion is connected to TIM5_CH4 Table 7 11 ADC4 extern...

Page 148: ...PE13 TIM1_CH4 PA11 PA11 PE14 TEAM1_BKIN PB12 PA6 PB5 PE15 TIM1_CH1N PB13 PA7 PB13 PE8 TIM1_CH2N PB14 PB0 PB14 PE10 TIM1_CH3N PB15 PB1 PB15 PE12 Table 7 17 TIM8 alternate function remapping Alternate...

Page 149: ...ship of DVP signals is shown in the following Table Table 7 20 DVP alternate function remapping Alternate function DVP_RMP 1 0 00 DVP_RMP 1 0 01 DVP_RMP 1 0 11 DVP_HSYNC PA1 PE2 PE2 DVP_VSYNC PA2 PE3...

Page 150: ...RT3_RX PB11 PC11 PD9 USART3_CK PB12 PC12 PD10 USART3_CTS PB13 PD11 USART3_RTS PB14 PD12 UARTx alternate function remapping UART4 5 6 7 interfaces have remapping function See the alternate remapping co...

Page 151: ...1 I2C1_SCL PB6 PB8 I2C1_SDA PB7 PB9 I2C1_SMBA PB5 7 2 5 12 2 I2C2 pin remapping See alternate remapping configuration register AFIO_RMP_CFG3 Table 7 29 I2C2 pin remapping Alternate function I2C2_RMP...

Page 152: ...e 7 33 SPI2 I2S2 pin remapping Alternate function SPI2_RMP 1 0 00 SPI2_RMP 1 0 01 SPI2_RMP 1 0 11 SPI2_NSS I2S2_WS PB12 PC6 PE10 SPI2_SCK I2S2_CK PB13 PC7 PE11 SPI2_MISO PB14 PC8 PE12 SPI2_MOSI I2S2_S...

Page 153: ...Alternate function QSPI_RMP 1 0 00 QSPI_RMP 1 0 01 QSPI_RMP 1 0 11 QSPI_NSS PA4 PF0 PC10 QSPI_CLK PA5 PF1 PC11 QSPI_IO0 PA6 PF2 PC12 QSPI_IO1 PA7 PF3 PD0 QSPI_ IO2 PC4 PF4 PD1 QSPI_ IO3 PC5 PF5 PD2 ET...

Page 154: ...iguration of peripherals Table 7 38 ADC DAC ADC DAC pin GPIO configuration ADC Analog mode DAC Analog mode Table 7 39 TIM1 TIM8 TIM1 TIM8 pin Configuration PAD configuration mode TIM1 8_CHx Input capt...

Page 155: ...DVP_D4 Input floating DVP_D5 Input floating DVP_D6 Input floating DVP_D7 Input floating Table 7 43 USART USART pin Configuration GPIO configuration USARTx_TX full duplex transmissions Push pull altern...

Page 156: ...r mode Floating input or input pull up or push pull alternate output Full duplex mode slave mode Push pull alternate output Simple bidirectional data line Master mode Unused can be used as general I O...

Page 157: ...utput QSPI_IO1 Push pull alternate output QSPI_IO0 Push pull alternate output QSPI_CLK Push pull alternate output QSPI_NSS Push pull alternate output Table 7 49 ETH MAC signal Pin configuration ETH_MD...

Page 158: ...g reset state ETH_MII_RXD2 Input floating reset state ETH_MII_RXD3 Input floating reset state Table 7 50 USB USB pin GPIO configuration USB_DM USB_DP Once the USB module is enabled these pins are auto...

Page 159: ...uence writing GPIOx_PH_CFG GPIOx_PL_CFG bits can be modified as long as PLOCK _ CFG 0 which is not affected by the configuration of GPIOx_PLOCK_CFG 15 0 PLOCKK_CFG 1 GPIOx_PH_CFG GPIOx_PL_CFG is contr...

Page 160: ...0 0 0 0 0 0 0 0 0 0 x B 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 x C D E F G 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 010h GPIOx_PBSC PBC15 PBC14 PBC13 PBC12 PBC11 PBC10 PBC9 PBC8 PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC...

Page 161: ...GPIOx_POD register 11 reserved When PMODE 1 0 00 output mode 00 General push pull output mode 01 General open drain output mode 10 Alternate function push pull output mode 11 Open drain output mode of...

Page 162: ...output mode 11 Open drain output mode of alternate function 29 28 25 24 21 20 17 16 13 12 9 8 5 4 1 0 PMODEy 1 0 Mode bit of port x y 8 15 00 input mode state after reset 01 output mode maximum speed...

Page 163: ...t setting clearing register GPIOx_PBSC Address offset 0x10 Reset value 0x0000 0000 Bit field Name Description 31 16 PBCy Clear bit y of port GPIOx y 0 15 These bits can only be written and operated as...

Page 164: ...OCKK_CFG Lock key This bit can be read at any time and it can only be modified by the key lock write sequence 0 Port configuration lock key is activated 1 The port configuration lock key is activated...

Page 165: ...DS_CFGy The drive capability configuration bit y of port GPIOx y 0 15 These bits can only be read or written in the form of 16 bit words 0 2mA 1 Controlled by PMODEy of GPIOx_PH_CFG GPIOx_PL_CFG PMOD...

Page 166: ...0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 014h AFIO_EXTI_CFG4 Reserved EXTI15_CFG 3 0 EXTI14_CFG 3 0 EXTI13_CFG 3 0 EXTI12_CFG 3 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01Ch Reserved 020h A...

Page 167: ...le 1 Output enable 6 4 PORT_SEL 2 0 Port selection bit Select the port used to output the event output signal of cortex 000 select port A 001 select port B 010 select port C 011 select port D 100 sele...

Page 168: ...ceiver of the external RMII interface 22 21 Reserved Reserved the reset value must be maintained 20 ADC2_ETRR ADC2 regular conversion external trigger remapping This bit can be set to 1 or set to 0 by...

Page 169: ...C_OUT 14 13 CAN1_RMP 1 0 CAN1 alternate function remapping These bits can be set to 1 or set to 0 by software to control the re mapping of the alternate functions CAN1_RX and CAN1_TX on products with...

Page 170: ...KIN PE15 CH1N PE8 CH2N PE10 CH3N PE12 5 4 USART3_RMP 1 0 Remapping of USART3 These bits can be set to 1 or set to 0 by software to control the image of the CTS RTS CK TX and RX alternate functions of...

Page 171: ...7 11 Remapping NSS PB2 SCK PE7 MISO PE8 MOSI PE9 7 4 4 AFIO external interrupt configuration register 1 AFIO_EXTI_CFG1 Address offset 0x08 Reset value 0x0000 0000 Bit field Name Description 31 16 Rese...

Page 172: ...bits can be read and written by software and used to select the input source of the EXTIx external interrupt EXTI4 configuration 0000 PA4 pin 0001 PB4 pin 0010 PC4 pin 0011 PD4 pin 0100 PE4 pin 0101...

Page 173: ...0101 Reserved 0110 Reserved EXTI9 configuration 0000 PA9 pin 0001 PB9 pin 0010 PC9 pin 0011 PD9 pin 0100 PE9 pin 0101 Reserved 0110 PG9 pin EXTI10 configuration 0000 PA10 pin 0001 PB10 pin 0010 PC10...

Page 174: ...served EXTI15 configuration 0000 PA15 pin 0001 PB15 pin 0011 PC15 pin 0011 PD15 pin 0100 PE15 pin 0101 PF15 pin 0110 Reserved 7 4 8 AFIO alternate remapping configuration register 3 AFIO_RMP_CFG3 Addr...

Page 175: ...01 Remapping TX PB13 RX PB14 10 Remapping TX PE8 RX PE9 11 Remapping TX PB8 RX PB9 21 20 UART4_RMP 1 0 Remapping of UART4 These bits can be set to 1 or set to 0 by software to control the image of th...

Page 176: ...SO and MOSI alternate functions of SPI3 on the GPIO port 00 No remapping NSS WS PA15 SCK CK PB3 MISO PB4 MOSI PB5 01 Remapping NSS WS PD2 SCK CK PC10 MISO PC11 MOSI PC12 10 Remapping NSS WS PD8 SCK CK...

Page 177: ...PF4 IO3 PF5 11 Remapping NSS PC10 SCK PC11 IO0 PC12 IO1 PD0 IO2 PD1 IO3 PD2 3 Reserved Reserved the reset value must be maintained 2 1 CAN2_RMP 1 0 CAN2 remapping This bit can be set to 1 or set to 0...

Page 178: ...D5 PB11 D6 PF14 D7 PF15 19 QSPI_XIP_EN QSPI XIP memory mapping mode enable control 0 Disable 1 Enable 18 Reserved Reserved the reset value must be maintained 17 ADC4_ETRR ADC4 regular conversion exte...

Page 179: ...ation 11 Remapping COMP6_OUT PB7 9 8 COMP5_RMP 1 0 Remapping of COMP5_OUT This bit can be set to 1 or 0 by software 00 No remapping COMP5_OUT PB0 01 Remapping COMP5_OUT PB11 10 Remapping COMP5_OUT PB6...

Page 180: ...set value must be maintained 23 EGB4_DET_EN EMC GB4 detection enable bit ground bounce detection 0 Disable 1 Enable 22 EGB3_DET_EN EMC GB3 detection enable bit 0 Disable 1 Enable 21 EGB2_DET_EN EMC GB...

Page 181: ...Enable 9 EGB2_RST_EN When EMC GB2 detects it the system resets the enable bit 0 Disable 1 Enable 8 EGB1_RST_EN When EMC GB1 detects it the system resets the enable bit 0 Disable 1 Enable 7 EGBN4_RST_E...

Page 182: ...ail info nationstech com Address Nations Tower 109 Baoshen Road Hi tech Park North Nanshan District Shenzhen 518057 P R China Bit field Name Description 1 Enable 0 ECLAMP1_RST_EN When EMC CLAMP1 detec...

Page 183: ...dently configurable DMA channels 8 channels each for DMA1 and DMA2 Support three transfer types which are Memory to Memory Memory to Peripheral and Peripheral to Memory Each DMA channel supports hardw...

Page 184: ...red by hardware peripherals or software and the DMA controller processes the request according to the priority level of the channel The data is read from the source address according to the configured...

Page 185: ...es an arbitration strategy to handle multiple requests from different channels The priority of each channel is programmable in the channel control register DMA_CHCFGx 4 levels of priority Very high pr...

Page 186: ...15 0 0x4 W B4 7 0 0x2 4 R B7B6 15 0 0x6 W B6 7 0 0x3 0x0 B0 0x1 B2 0x2 B4 0x3 B6 16 16 4 0x0 B1B0 0x2 B3B2 0x4 B5B4 0x6 B7B6 1 R B1B0 15 0 0x0 W B1B0 15 0 0x0 2 R B3B2 15 0 0x2 W B3B2 15 0 0x2 3 R B5...

Page 187: ...o extra bits will be padded with 0 8 4 5 Peripheral Memory address incrementation DMA_CHCFGx PINC and DMA_CHCFGx MINC respectively control whether the peripheral address and memory address are enabled...

Page 188: ...in each DMA channel configuration register Flow control is used to control source destination and direction of DMA channel Table 8 2 Flow control table DMA_CHCFGx MEM2MEM DMA_CHCFGx DIR Source Destina...

Page 189: ...g clear bit is set Half transfer interrupt An interrupt is generated when half of the channel data is transferred Interrupt is a level signal Each channel has its dedicated interrupt interrupt mask co...

Page 190: ...TIM3_CH3 Hardware request 3 SPI1_TX USART3_RX TIM1_CH2 TIM3_CH4 TIM3_UP Hardware request 4 SPI2 I2S2_RX USART1_TX I2C2_TX TIM1_CH4 TIM1_TRIG TIM1_COM TIM4_CH3 Hardware request 5 Hardware request 6 USA...

Page 191: ...Channel 7 Channel 8 TIM2 TIM2_CH3 TIM2_UP TIM2_CH1 TIM2_CH2 TIM2_CH4 TIM3 TIM3_CH3 TIM3_CH4 TIM3_UP TIM3_CH1 TIM3_TRIG TIM4 TIM4_CH1 TIM4_CH2 TIM4_CH3 TIM4_UP DMA2 controller The DMA2 request mapping...

Page 192: ...4 Hardware request 5 Hardware request 6 Hardware request 7 Hardware request 8 Hardware request 1 Peripheral request signal Channel 1 Software trigger MEM2MEM bit Channel 1 enable bit Channel 2 Softwar...

Page 193: ...2 CTXCF2 CGLBF2 CERRF1 CHTXF1 CTXCF1 CGLBF1 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 008h DMA_CHCFG1 Reserved MEM2MEM PRIOLVL 1 0 MSIZE 1 0 PSIZE 1 0 MINC PINC CIRC...

Page 194: ...lue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 068h DMA_CHSEL5 Reserved CH_SEL 5 0 Reset Value 0 0 0 0 0 0 06Ch DMA_CHCFG6 Reserved MEM2MEM PRIOLVL 1 0 MSIZE 1 0 PSIZE 1 0 MINC PI...

Page 195: ...alf transfer flag for channel x x 1 8 Hardware sets this bit when half transfer is done This bit is cleared by software by writing 1 to DMA_INTCLR CHTXFx bit 0 Half transfer not yet done on channel x...

Page 196: ...hannel 29 25 21 17 13 9 5 1 CTXCFx Clear transfer complete flag for channel x x 1 8 Software can set this bit to clear TXCF of corresponding channel 0 No action 1 Reset DMA_INTSTS TXCF bit of correspo...

Page 197: ...le memory address increment mode 0 Memory address won t increase with each transfer 1 Memory address increase with each transfer 6 PINC Peripheral increment mode Software can enable disable peripheral...

Page 198: ...0c 20 x 1 Reset value 0x0000 0000 This register can only be written if the channel is disabled DMA_CHCFGx CHEN 0 Bit field Name Description 31 16 Reserved Reserved the reset value must be maintained 1...

Page 199: ...000 This register can only be written if the channel is disabled DMA_CHCFGx CHEN 0 Bit field Name Description 31 0 ADDR ADDR Memory address Memory starting address for DMA to read write from to Increm...

Page 200: ...to the DMA request of ADC1 Bit field Name Description 31 6 Reserved Reserved the reset value must be maintained 5 0 CH_SEL 5 0 DMA1 channel request selection 40 UART5_RX 39 ADC2 38 I2C1_RX 37 TIM4_UP...

Page 201: ...is only valid when the channel MAP is enabled DMA_CHMAPEN MAP_EN 1 This register is used to manage the DMA2 channel mapped by the DMA2 peripheral request Note After the channel MAP is enabled DMA cha...

Page 202: ...I2S3_RX 3 TIM8_UP 2 TIM8_CH3 1 TIM5_TRIG 0 TIM5_CH4 8 5 10 DMA channel MAP enable register DMA_CHMAPEN Address offset 0xA8 Reset value 0x0000 0000 Note After the MAP is enabled DMA will respond to the...

Page 203: ...s Technologies Inc Tel 86 755 86309900 Email info nationstech com Address Nations Tower 109 Baoshen Road Hi tech Park North Nanshan District Shenzhen 518057 P R China Bit field Name Description 1 Enab...

Page 204: ...ADC3 supports 15 external channels and ADC4 supports 13 external channels Support 12 bit 10 bit 8 bit 6 bit resolution configurable The highest sampling rate 5 14MSPS under 12bit resolution The highe...

Page 205: ...ADCx_IN15 Gpio Ports Analog channel multiplexing VTS VREFINT ADCCLK ADC prescaler Data bus Injected data registers 4 x 16 bits Regular data register 16 bits Data register Analog watchdog Interrupt ge...

Page 206: ...same otherwise the ADC accuracy will be affected 4 External channel reference data sheet 9 3 1 ADC clock An ADC requires three clocks HCLK ADC_CLK and ADC_1MCLK HCLK is used for the register access AD...

Page 207: ...checked by polling the ADC_CTRL3 PDRDY bit When the ADC is disabled the default mode is power down In this mode as long as the power is on there is no need to re calibrate and the calibration value is...

Page 208: ...e conversions up to a maximum of 16 The ADC_RSEQx registers specify the regular channels and the conversion order of the regular channels The ADC_RSEQ1 LEN 3 0 bits specified regular channel sequence...

Page 209: ...3 VINN 3 VINP 4 VINN 4 VINP 5 VINN 5 VINP 6 VINN 6 VINP 7 VINN 7 VINP 8 VINN 8 VINP 9 VINN 9 VINP 10 VINN 10 VINP 11 VINN 11 VINP 12 VINN 12 VINP 13 VINN 13 VINN 14 VINP 15 VINN 15 VINP 16 VINN 16 VI...

Page 210: ...P 0 VINN 0 VINP 1 VINN 1 VINP 2 VINN 2 VINP 3 VINN 3 VINP 4 VINN 4 VINP 5 VINN 5 VINP 6 VINN 6 VINP 7 VINN 7 VINP 8 VINN 8 VINP 9 VINN 9 VINP 10 VINN 10 VINP 11 VINN 11 VINP 12 VINN 12 VINP 13 VINN 13...

Page 211: ...end flag ADC_STS JENDC will be set to 1 If the injection channel conversion end interrupt enable ADC_CTRL1 JENDCIEN bit is set to 1 an interrupt will be generated at this time and the converted data w...

Page 212: ...figuring ADC_WDGHIGH HTH and the low threshold of the analog watchdog can be set by configuring ADC_WDGLOW LTH The threshold of the analog watchdog has nothing to do with the way of data alignment bec...

Page 213: ...ADC_CTRL1 AUTOJC bit is set then the Injected channels are automatically converted following the regular channels mentioned by ADC_RSEQ and ADC_JSEQx A single trigger can conver up to 16 4 channels S...

Page 214: ...he regular sequence and then stop until the next trigger signal is generated Next trigger will continue to convert n channels from the point where the previous conversion stopped until all channels of...

Page 215: ...rogram sets the ADC_CTRL2 ENCAL bit to 1 to start self calibration During the calibration the ADC_CTRL2 ENCAL bit remains 1 After the calibration the ADC_CTRL2 ENCAL bit is cleared by hardware and the...

Page 216: ...t voltage in the specified sampling cycle For different channels you can select different sampling time The total conversion time is calculated as follows TCONV Sampling time 12 5 cycles Example ADCCL...

Page 217: ...1 SWSTRRCH Software control bit For the injection sequence the software sets the ADC_CTRL2 EXTJTRIG bit to 1 then the injection channel can use the rising edge of the external event to trigger the sta...

Page 218: ...st it will transfer the converted data from the ADC_DAT register to the destination address specified by the user Note In independent ADC mode ADC1 ADC2 ADC3 ADC4 have DMA function In dual ADC mode th...

Page 219: ...ta will be stored in the ADC_DAT register The high half word of ADC_DAT is the conversion data of ADC2 The low half word of ADC_DAT is the conversion data of ADC1 and 32 bit DMA can be used to transfe...

Page 220: ...ternal trigger comes from the multiplexer of ADC1 determined by ADC_CTRL2 EXTJSEL 2 0 ADC2 will be triggered synchronously If ADC1 or ADC2 sets ADC_CTRL1 JENDCIEN a JENDC interrupt will be generated w...

Page 221: ...nce will be converted continuously The converted data will be stored in the ADC_DAT register The high halfword of ADC_DAT is the conversion data of ADC2 and the low halfword of ADC_DAT is the conversi...

Page 222: ...y converts the regular sequence without the need to set ADC_CTRL2 CTU The converted data will be stored in the ADC_DAT register The high half word of ADC_DAT is the conversion data of ADC2 and the low...

Page 223: ...nverted when the second trigger is generated all injection channels of ADC2 are converted and so on If ADC1 or ADC2 sets ADC_CTRL1 JENDCIEN a JENDC interrupt will be generated when the conversion of t...

Page 224: ...on of the synchronous injection channel can interrupt the transition of the synchronous regular channel Note In this mode the sequence of synchronous conversion of ADC1 and ADC2 needs to be set to the...

Page 225: ...er occurs during injection transition 9 9 9 Mixed synchronous injection mode alternate mode In this mode when the injection trigger occurs the alternate conversion will be interrupted the injection co...

Page 226: ...digital value by the ADC_IN16 channel When the temperature sensor is working the ideal sampling time is 17 1us when the temperature sensor is not working the ADC_CTR2 TEMPEN bit can be cleared by soft...

Page 227: ...re and Average slope of a VSENSE curve mV C or V C Toffset empirical value for temperature error compensation C Refer to the values of V30 and Avg_Slope in the electrical characteristics chapter of th...

Page 228: ...DIEN AWDGCH Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 008h ADC_CTRL2 Reserved TEMPEN SWSTRRCH SWSTRJCH EXTRTRIG EXTRSEL 2 0 Reserved EXTJTRIG EXTJSEL ALIG Reserved EN...

Page 229: ...048h ADC_JDAT4 Reserved JDAT4 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 04Ch ADC_DAT Reserved DAT 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 050h ADC_DIFSEL Reserved DIFSEL 18 0 Reserved...

Page 230: ...version This bit is set by hardware at the end of all injection sequence channel conversions and cleared by software 0 Conversion is not complete 1 Conversion is complete 1 ENDC Conversion sequence ch...

Page 231: ...erved in ADC2 and ADC4 Changing the channel configuration in dual ADC mode will cause a restart condition It is recommended to turn off the dual ADC mode before changing the configuration to avoid syn...

Page 232: ...DCIEN Interrupt enable for injected channels This bit is set and cleared by the software to disallow or allow interrupts after all injection channel conversions have finished 0 Disable JENDC interrupt...

Page 233: ...ion of a set of regular channels 0 Reset state 1 Starts converting the regular channel 21 SWSTRJCH Start conversion of injected channels This bit is set by the software to initiate the conversion and...

Page 234: ...gger configuration for ADC1 and ADC2 000 TIM1_TRGO event 100 TIM3_CC4 event 001 TIM1_CC4 event 101 TIM4_TRGO event 010 TIM2_TRGO event 110 EXTI line 15 TIM8_CC4 event 011 TIM2_CC1 event 111 SWSTRRCH T...

Page 235: ...the conversion will not be triggered This is to prevent the wrong conversion from being triggered 9 12 5 ADC sampling time register 1 ADC_SAMPT1 Address offset 0x0C Reset value 0x0000 0000 Bit field...

Page 236: ...cycles 110 71 5 cycles 011 28 5 cycles 111 239 5 cycles ADC_SAMPT3 SAMPSEL 1 the sampling time is set as follows 000 1 5 cycles 100 19 5 cycles 001 2 5 cycles 101 61 5 cycles 010 4 5 cycles 110 181 5...

Page 237: ...ter ADC_WDGLOW Address offset 0x28 Reset value 0x0000 0000 Bit field Name Description 31 12 Reserved Reserved the reset value must be maintained 11 0 LTH 11 0 Analog watchdog low threshold These bits...

Page 238: ...version in regular sequence 9 12 11 ADC regular sequence register 2 ADC_RSEQ2 Address offset 0x30 Reset value 0x0000 0000 Bit field Name Description 31 30 Reserved Reserved the reset value must be mai...

Page 239: ...value 0x0000 0000 Bit field Name Description 31 22 Reserved Reserved the reset value must be maintained 21 20 JLEN 1 0 Injected sequence length These bits are software defined as the number of channe...

Page 240: ...ted channel The data is left aligned or right aligned 9 12 15 ADC regulars data register ADC_DAT Address offset 0x4C Reset value 0x0000 0000 Bit field Name Description 31 16 ADC2DAT 15 0 Data converte...

Page 241: ...te the hardware will update it according to the calibration coefficient Software can write these bits with a new calibration factor If the new calibration coefficient is different from the current coe...

Page 242: ...is disabled the ADC enters low power mode 1 When the ADC is disabled the ADC enters deep sleep mode 9 JENDCAIEN Interrupt enable for any injected channels This bit is set and cleared by the software...

Page 243: ...Data resolution This bit is set and cleared by the software to select the resolution of the conversion 00 6 bits 01 8 bits 10 10 bits 11 12 bits 9 12 19 ADC sampling time register 3 ADC_SAMPT3 Address...

Page 244: ...d The DAC output channel has 2 with independent converter Both channels can be configured to convert independently or to convert simultaneously and update the output simultaneously VREF is used as the...

Page 245: ...ltage VDDA Analog power Input analog power VSSA Analog power ground Input analog power ground DACx_OUT DAC analog output Analog output signal Note When the DACx is enabled PA4 or PA5 needs to be confi...

Page 246: ...the data alignment configuration the corresponding registers of the data configuration are as follows When the DAC outputs independently there are 3 cases When the configuration data is written to th...

Page 247: ...ernal data storage register When the configuration data is written to the DAC_DR12DCH register the DAC1 data is written to DAC_DR12DCH 15 4 Actually stored in the register DACCH1D 11 0 bits DACCH1D is...

Page 248: ...trigger Trigger source Type TSEL 2 0 Timer 6 TRGO events Internal signal from the on chip timer 000 Timer 8 TRGO events 001 Timer 7 TRGO events 010 Timer 5 TRGO events 011 Timer 2 TRGO events 100 Tim...

Page 249: ...alignment data hold register will be transferred to the DAC_DATOx register after three APB1 cycles according to the selected trigger event when the hardware trigger occurs When the software trigger o...

Page 250: ...ar when two DACs are turned on Note DMA requests for DAC have no accumulative function and when the second external trigger occurs before the response to the first external trigger the second DMA requ...

Page 251: ...tude of the triangle wave can be selected by configuring DAC_CTRL MAxSEL 3 0 The value of the internal triangle wave counter is added to the value of the DAC alignment data holding register and writte...

Page 252: ...er DAC can still operate independently For details please refer to the following chapter description 10 4 1 Independent trigger without waveform generator The configuration process is as follows Confi...

Page 253: ...figure DAC_CTRL T1EN and DAC_CTRL T2EN to enable trigger enable of DAC1 and DAC2 Configure DAC_CTRL T1SEL 2 0 and DAC_CTRL T2SEL 2 0 as different values to select different trigger sources Configure D...

Page 254: ...ure DAC_CTRL W1EN 1 0 and DAC_CTRL W2EN 1 0 as 1x to select the triangle wave generation enable Configure DAC_CTRL MA1SEL3 0 and DAC_CTRL MA2SEL3 0 as different values to get different triangle wave a...

Page 255: ...DAC_CTRL W2EN 1 0 as 01 to select noise generation enable Configure DAC_CTRL MA1SEL3 0 and DAC_CTRL MA2SEL3 0 to the same value to get the same LFSR register mask bit Put the data to be converted int...

Page 256: ...litude value of DAC1 is added to the value of the corresponding data holding register The added value is transferred to the register DAC_DATO1 after a delay of 3 APB1 clock cycles and the counter valu...

Page 257: ...H1D 11 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 00Ch DAC_DL12CH1 Reserved DACCH1D 11 0 Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 010h DAC_DR8CH1 Reserved DACCH1D 7 0 Reset Value 0 0 0 0 0 0 0 0 014h D...

Page 258: ...mplitude equals 63 0110 unmasked LFSR bit 6 0 triangular amplitude equals 127 0111 unmasked LFSR bit 7 0 triangular amplitude equals 255 1000 unmasked LFSR bit 8 0 triangular amplitude equals 511 1001...

Page 259: ...ude equal 3 0010 unmasked LFSR bit 2 0 triangular amplitude equals 7 0011 unmasked LFSR bit 3 0 triangular amplitude equals 15 0100 unmasked LFSR bit 4 0 triangular amplitude equals 31 0101 unmasked L...

Page 260: ...igger register DAC_SOTTR Offset address 0x04 Reset value 0x0000 0000 Bit field Name Description 31 2 Reserved Reserved the reset value must be maintained 1 TR2EN The DAC2 software trigger This bit is...

Page 261: ...AC1 converts the data 10 5 5 12 bit left aligned data hold register for DAC1 DAC_DL12CH1 Offset address 0x0c Reset value 0x0000 0000 Bit field Name Description 31 16 Reserved Reserved the reset value...

Page 262: ...1 12 Reserved Reserved the reset value must be maintained 11 0 DACCH2D 11 0 12 bit right aligned data for DAC2 The bits are configured by the software and the DAC2 converts the data 10 5 8 12 bit left...

Page 263: ...DAC_DR12DCH Offset address 0x20 Reset value 0x0000 0000 Bit field Name Description 31 28 Reserved Retained the reset value must be maintained 27 16 DACCH2D 11 0 12 bit right aligned data for DAC2 The...

Page 264: ...0 5 12 8 bit right aligned data hold register for dual DAC DAC_DR8DCH Offset address 0x28 Reset value 0x0000 0000 Bit field Name Description 31 16 Reserved Retained the reset value must be maintained...

Page 265: ...Shenzhen 518057 P R China 10 5 14 DAC2 data output register DAC_DATO2 Offset address 0x30 Reset value 0x0000 0000 Bit field Name Description 31 12 Reserved Retained the reset value must be maintained...

Page 266: ...ctor can be configured with any value between 1 and 65536 Programmable Repetition Counter TIM1 up to 6 channels TIM8 up to 6 channels 4 capture compare channels the working modes are PWM output ouput...

Page 267: ...IMx_CTRL1 CNTEN bit is set The counter starts counting one clock cycle after the TIMx_CTRL1 CNTEN bit is set TI2FP1 TI2FP2 TI1FP2 TI3FP3 TI1FP1 TI4FP4 XOR TI2 TI3 TI1 TI4 Polarity selection BRK IC4 IC...

Page 268: ...overflow event is generated If the TIMx_CTRL1 UPRS bit select update request and the TIMx_EVTGEN UDGN bit are set an update event UEV will generate And TIMx_STS UDITF will not be set by hardware there...

Page 269: ...ll still be cleared and the prescaler counter will also be set to 0 but the prescaler value will remain unchanged The figure below shows some examples of the counter behavior and the update flags for...

Page 270: ...ck CK_CNT Counter register Update event UEV Update interrupt flag UDITF Write a new value in TIMx_AR 32 31 33 34 35 36 00 01 02 03 FF 36 04 05 06 07 Counter overflow Auto reload preload register Auto...

Page 271: ...2 N Center aligned mode In center aligned mode the counter increments from 0 to the value TIMx_AR 1 a counter overflow event is generated It then counts down from the auto reload value TIMx_AR to 1 an...

Page 272: ...note if the update source is a counter overflow auto reload update before reloading the counter Figure 11 6 Timing diagram of the Center aligned internal clock divided factor 2 N Figure 11 7 A center...

Page 273: ...s means that data is transferred from the preload registers to the shadow registers every N 1 counter overflow or CK_PSC CNTEN Timer clock CK_CNT Counter register Update event UEV 05 06 04 03 02 01 00...

Page 274: ...occurs In center aligned mode each time the counter overflows or underflows Its repetition rate is defined by the value of the TIMx_REPCNT register Repetition counters feature automatic reloading The...

Page 275: ...count sequence diagram in center aligned mode Software clear 34 35 36 00 01 35 36 00 01 35 36 00 01 35 36 00 01 35 36 00 01 35 36 00 01 33 CK_PSC CNTEN Timer clock CK_CNT Underflow Overflow UDITF UDI...

Page 276: ...Internal clock source CK_INT When the TIMx_SMCTRL SMSEL is equal to 000 the slave mode controller is disabled The three control bits TIMx_CTRL1 CNTEN TIMx_CTRL1 DIR TIMx_EVTGEN UDGN can only be change...

Page 277: ...g TIMx_CCMOD1 IC2F 3 0 if filter is not needed keep IC2F bit at 0000 Configure TIMx_SMCTRL SMSEL equal to 111 select timer external clock mode 1 Configure TIMx_SMCTRL TSEL equal to 110 select TI2 as t...

Page 278: ...example use the following configuration steps to make the up counter count every 2 rising edges on ETR Since no filter is needed in this case make TIMx_SMCTRL EXTF 3 0 equal to 0000 Configure the pre...

Page 279: ...nels Capture compare channels include capture compare registers and shadow registers The input section consists of digital filters multiplexers and prescalers The output section includes comparators a...

Page 280: ...an intermediate waveform OCxRef active high as reference The polarity acts at the end of the chain fDTS Filter Down counter TIMx_CCMOD1 IC1F 3 0 TI1 Edge Detector TIMx_CCEN CC1P From channel 2 From s...

Page 281: ...main circuit S R From time base unit Read CCDAT1H TIM1_EVTGEN CC1GN Read in progress Input mode S R Read CCDAT1L Output mode CC1SEL 1 CC1SEL 0 UEV Write in progress APB Bus MCU Peripheral interface Ca...

Page 282: ...pt or DMA request if the corresponding interrupt enable is pulled high TIM1_CCMOD1 OC1CEN TIM1_CCMOD1 OC1M D 2 0 CNT CCR1 CNT CCR1 TIM1_CCMOD1 OC1CEN TIM1_CCMOD1 OC1MD 2 0 OC1ERF OCxERF Dead time gene...

Page 283: ...w level are detected we can validate the transition on TI1 Then configure TIMx_CCMOD1 IC1F to 0011 By configuring TIMx_CCEN CC1P 0 select the rising edge as the valid transition polarity on the TI1 ch...

Page 284: ...with the TIMx_CH1 TIMx_CH2 signals 11 3 8 Forced output mode Software can force output compare signals to active or inactive level directly in output mode TIMx_CCMODx CCxSEL 00 User can set TIMx_CCMOD...

Page 285: ...user set TIMx_DINTEN CCxIEN a corresponding interrupt will be generated If user set TIMx_DINTEN CCxDEN and set TIMx_CTRL2 CCDSEL to select DMA request and DMA request will be sent User can set TIMx_C...

Page 286: ...xP On the other hand to enable the output of OCx user need to set the combination of the value of CCxEN CCxNEN MOEN OSSI and OSSR in TIMx_CCEN and TIMx_BKDT The values of TIMx_CNT and TIMx_CCDATx are...

Page 287: ...alue of TIMx_CTRL1 DIR that the counter counts up or down Cautions that the DIR and CAMSEL bits should not be changed at the same time User should not write the counter while running in center aligned...

Page 288: ...Up counting User can set TIMx_CTRL1 DIR 0 to make counter counts up Here is an example for PWM mode1 When TIMx_CNT TIMx_CCDATx the reference PWM signal OCxREF is high Otherwise it will be low If the c...

Page 289: ...ed and a pulse tPULSE with a controllable pulse width is generated after a controllable delay tDELAY The output mode needs to be configured as output compare mode or PWM mode After selecting one pulse...

Page 290: ...be converted to the same level as the comparison match occurs immediately regardless of the comparison result OCxFEN fast enable only takes effect when the channel mode is configured for PWM1 and PWM...

Page 291: ...Mx_BKDT OSSR When switching to the IDLE state the dead time will be activated If user set TIMx_CCEN CCxEN and TIMx_CCEN CCxNEN at the same time a dead time will be insert If there is a break circuit t...

Page 292: ...inactive level user can use this function to send a specific waveform such as PWM or static active level User can also use this function to set both outputs in their inactive level or both outputs ac...

Page 293: ...g edge of MOEN can be asynchronous so between the actual signal and the synchronous control bit there set a resynchronization circuit This circuit will cause a delay between the asynchronous and the s...

Page 294: ...r other security components When the break input is active TIMx_BKDT MOEN cannot be set automatically or by software at the same time and the TIMx_STS BITF cannot be cleared Because the break inputs a...

Page 295: ...prescaler updates the preload registers TIMx_AR TIMx_CCDATx and generates the update event UEV TIMx_CTRL1 UPRS 0 The following is an example of a reset mode 1 Channel 1 is configured as input to detec...

Page 296: ...due to the resynchronization circuit on TI2 input Figure 11 28 Control circuit in Trigger mode Slave mode Gated mode In gate control mode the level polarity of the input port can control whether the...

Page 297: ...his time the trigger selection needs to select non ETRF TIMx_SMCTRL TSEL 111 Here is an example 1 Channel 1 is configured as input to detect the rising edge of TI1 TIMx_CCMOD1 CC1SEL 01 TIMx_CCEN CC1P...

Page 298: ...in advance the preloaded bits are OCxMD CCxEN and CCxNEN When a COM commutation event occurs the OCxMD CCxEN and CCxNEN preload bits are transferred to the shadow register bits COM commutation event...

Page 299: ...TI2 at the same time TIMx_SMCTRL SMSEL 011 The encoder interface is equivalent to using an external clock with direction selection and the counter only counts continuously between 0 and the auto relo...

Page 300: ...down Counting up Counting on TI1 and TI2 High Counting down Counting up Counting up Counting down Low Counting up Counting down Counting down Counting up Here is an example of an encoder with dual ed...

Page 301: ...ail info nationstech com Address Nations Tower 109 Baoshen Road Hi tech Park North Nanshan District Shenzhen 518057 P R China Figure 11 33 Encoder interface mode example with IC1FP1 polarity inverted...

Page 302: ...EL 100 any change in the Hall 3 inputs will trigger the counter to recount so it is used as a time reference the capture compare channel 1 is configured to capture the TRC signal in capture mode TIMx_...

Page 303: ...n Road Hi tech Park North Nanshan District Shenzhen 518057 P R China Figure 11 34 Example of Hall sensor interface TI1 Counter CNT CCDAT2 OC1 OC1N Va OC2 OC2N OC3 OC3N Write CCxEN CCxNEN and OCxMD for...

Page 304: ...0 0 0 0 0 0 0 0 0 0 00Ch TIMx_DINTEN Reserved TDEN COMDEN CC4DEN CC3DEN CC2DEN CC1DEN UDEN BIEN TIEN COMIEN CC4IEN CC3IEN CC2IEN CC1IEN UIEN Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 010h TIMx_STS Re...

Page 305: ...0 0 0 0 0 0 0 0 0 0 0 0 03Ch TIMx_CCDAT3 Reserved CCDAT3 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 040h TIMx_CCDAT4 Reserved CCDAT4 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 044h TIMx_BK...

Page 306: ...1 selection 0 Select external CH1 signal from IOM 1 Select internal CH1 signal from COMP Note Before operating this bit the extended mode of the chip must be turned on set PWR_CTRL3 EXMODE 10 IOMBKPEN...

Page 307: ...is used to select the UEV event sources by software 0 If update interrupt or DMA request is enabled any of the following events will generate an update interrupt or DMA request Counter overflow underf...

Page 308: ...t Idle state 1 OC1N Output 0 When TIMx_BKDT MOEN 0 after dead time OC1N 0 1 When TIMx_BKDT MOEN 0 after dead time OC1N 1 8 OI1 Output Idle state 1 0 When TIMx_BKDT MOEN 0 if OC1N is implemented after...

Page 309: ...ompare DMA selection 0 When a CCx event occurs a DMA request for CCx is sent 1 When an update event occurs a DMA request for CCx is sent 2 CCUSEL Capture compare control update selection 0 If TIMx_CTR...

Page 310: ...of the external trigger signal ETRP must be at most 1 4 of TIMxCLK frequency When a faster external clock is input a prescaler can be used to reduce the frequency of ETRP 00 Prescaler disable 01 ETRP...

Page 311: ...en directly by the internal clock 001 Encoder mode 1 According to the level of TI2FP2 the counter up counting or down counting on the edge of TI1FP1 010 Encoder mode 2 According to the level of TI1FP1...

Page 312: ...e capture compare 4 DMA request 11 CC3DEN Capture Compare 3 DMA request enable 0 Disable capture compare 3 DMA request 1 Enable capture compare 3 DMA request 10 CC2DEN Capture Compare 2 DMA request en...

Page 313: ...compare 1 interrupt 1 Enables capture comparing 1 interrupt 0 UIEN Update interrupt enable 0 Disable update interrupt 1 Enables update interrupt 11 4 6 Status registers TIMx_STS Offset address 0x10 Re...

Page 314: ...No trigger event occurred 1 Trigger interrupt occurred 5 COMITF COM interrupt flag This bit is set by hardware once a COM event is generated when TIMx_CCEN CCxEN TIMx_CCEN CCxNEN TIMx_CCMOD1 OCxMD ha...

Page 315: ...o update event occurred 1 Update interrupt occurred 11 4 7 Event generation registers TIMx_EVTGEN Offset address 0x14 Reset values 0x0000 Bit field Name Description 15 8 Reserved Reserved the reset va...

Page 316: ...lag will be pulled high if the corresponding interrupt and DMA are enabled the corresponding interrupt and DMA will be generated If The TIMx_STS CC1ITF is already pulled high pull TIMx_STS CC1OCF high...

Page 317: ...he output reference signal OC1REF which determines the values of OC1 and OC1N and is valid at high levels while the active levels of OC1 and OC1N depend on the TIMx_CCEN CC1P and TIMx_CCEN CC1NP bits...

Page 318: ...n match on CC1 output Therefore OC is set to the comparison level regardless of the comparison result The delay time for sampling the trigger input and activating the CC1 output is reduced to 3 clock...

Page 319: ...S 16 N 5 1011 fSAMPLING fDTS 16 N 6 1100 fSAMPLING fDTS 16 N 8 1101 fSAMPLING fDTS 32 N 5 1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 3 2 IC1PSC 1 0 Input Capture 1 prescaler These bits are...

Page 320: ...10 CC4 channel is configured as input IC4 is mapped on TI3 11 CC4 channel is configured as input IC4 is mapped on TRC This mode is only active when the internal trigger input is selected by TIMx_SMCTR...

Page 321: ...3 0 Input Capture 3 filter 3 2 IC3PSC 1 0 Input Capture 3 Prescaler 1 0 CC3SEL 1 0 Capture compare 3 selection These bits are used to select the input output and input mapping of the channel 00 CC3 c...

Page 322: ...y See TIMx_CCEN CC1NP description 6 CC2NEN Capture Compare 2 complementary output enable See TIMx_CCEN CC1NEN description 5 CC2P Capture Compare 2 output polarity See TIMx_CCEN CC1P description 4 CC2E...

Page 323: ...1 Enable capture Table 11 4 Output control bits of complementary OCx and OCxN channels with break function Control bits Output state1 MOENOSSI OSSR CCxEN CCxNENOCx Output state OCxN Output state 1 X 0...

Page 324: ...If both outputs of a channel are not used CCxEN CCxNEN 0 OIx OIxN CCxP and CCxNP must all be cleared Note The status of external I O pins connected to complementary OCx and OCxN channels depends on t...

Page 325: ...epetition counter value Repetition counter is used to generate the update event or update the timer registers only after a given number N 1 cycles of the counter where N is the value of TIMx_REPCNT RE...

Page 326: ...dable and writable 11 4 16 Capture compare register 2 TIMx_CCDAT2 Offset address 0x38 Reset value 0x0000 Bit field Name Description 15 0 CCDAT2 15 0 Capture Compare 2 values CC2 channel is configured...

Page 327: ...e register CCDAT3 and CCDDAT3 are readable and writable 11 4 18 Capture compare register 4 TIMx_CCDAT4 Offset address 0x40 Reset value 0x0000 Bit field Name Description 15 0 CCDAT4 15 0 Capture Compar...

Page 328: ...ny write to this bit requires an APB clock delay to take effect 12 BKEN Break enable 0 Disable brake input BRK and CCS clock failure events 1 Enable brake input BRK and CCS clock failure events Note A...

Page 329: ...d in output mode also enable write protection Note After the system reset the LCKCFG bit can only be written once Once written to the TIMx_BKDT register LCKCFG will be protected until the next reset 7...

Page 330: ..._CTRL1 00001 TIMx_CTRL2 00010 TIMx_SMCTRL 10001 TIMx_BKDT 10010 TIMx_DCTRL 11 4 21 DMA transfer buffer register TIMx_DADDR Offset address 0x4C Reset value 0x0000 Bit field Name Description 15 0 BURST...

Page 331: ...ompare mode registers 3 TIMx_CCMOD3 Offset address 0x54 Reset value 0x0000 Bit field Name Description 15 OC6CEN Output compare 6 clear enable 14 12 OC6MD 2 0 Output compare 6 mode 11 OC6PEN Output com...

Page 332: ...ve register only when an update event occurs TIM1_CC5 and TIM8_CC5 is used for comparator blanking 11 4 24 Capture compare register 6 TIMx_CCDAT6 Offset address 0x5C Reset value 0x0000 Bit field Name...

Page 333: ...ize up counting down counting up down counting 16 bit programmable prescaler The frequency division factor can be configured with any value between 1 and 65536 TIM2 TIM3 TIM4 and TIM5 up to 4 channels...

Page 334: ...it can be generated by software when TIMx_CTRL1 UPDIS 0 The counter CK_CNT is valid only when the TIMx_CTRL1 CNTEN bit is set The counter starts counting one clock cycle after the TIMx_CTRL1 CNTEN bi...

Page 335: ...te And TIMx_STS UDITF will not be set by hardware therefore no update interrupts or update DMA requests are generated This setting is used in scenarios where you want to clear the counter but do not w...

Page 336: ...d The figure below shows some examples of the counter behavior and the update flags for different division factors in the up counting mode Figure 12 3 Timing diagram of up counting The internal clock...

Page 337: ...ck CK_CNT Counter register Update event UEV Update interrupt flag UDITF Write a new value in TIMx_AR 32 31 33 34 35 36 00 01 02 03 FF 36 04 05 06 07 Counter overflow Auto reload preload register Auto...

Page 338: ...2 N Center aligned mode In center aligned mode the counter increments from 0 to the value TIMx_AR 1 a counter overflow event is generated It then counts down from the auto reload value TIMx_AR to 1 an...

Page 339: ...arts from 0 as does the prescaler s counter Please note if the update source is a counter overflow auto reload update before reloading the counter Figure 12 6 Timing diagram of the Center aligned inte...

Page 340: ...inds of external clock mode CK_PSC CNTEN Timer clock CK_CNT Counter register Update event UEV 05 06 04 03 02 01 00 01 02 03 04 05 06 07 Counter underflow Update interrupt flag UDITF Auto reload preloa...

Page 341: ...L is equal to 000 the slave mode controller is disabled The three control bits TIMx_CTRL1 CNTEN TIMx_CTRL1 DIR TIMx_EVTGEN UDGN can only be changed by software except TIMx_EVTGEN UDGN which remains cl...

Page 342: ...TIMx_CCMOD1 IC2F 3 0 if filter is not needed keep IC2F bit at 0000 Configure TIMx_SMCTRL SMSEL equal to 111 select timer external clock mode 1 Configure TIMx_SMCTRL TSEL equal to 110 select TI2 as th...

Page 343: ...ion steps to make the up counter count every 2 rising edges on ETR Since no filter is needed in this case make TIMx_SMCTRL EXTF 3 0 equal to 0000 Configure the prescaler by making TIMx_SMCTRL EXTPS 1...

Page 344: ...capture compare registers and shadow registers The input section consists of digital filters multiplexers and prescalers The output section includes comparators and output controls The input signal T...

Page 345: ...an intermediate waveform OCxRef active high as reference The polarity acts at the end of the chain fDTS Filter Down counter TIMx_CCMOD1 IC1F 3 0 TI1 Edge Detector TIMx_CCEN CC1P From channel 2 From s...

Page 346: ...main circuit S R From time base unit Read CCDAT1H TIM1_EVTGEN CC1GN Read in progress Input mode S R Read CCDAT1L Output mode CC1SEL 1 CC1SEL 0 UEV Write in progress APB Bus MCU Peripheral interface Ca...

Page 347: ...an interrupt or DMA request if the corresponding interrupt enable is pulled high The TIMx_STS CCxITF bit is set by hardware when a capture event occurs and is cleared by software or by reading the TIM...

Page 348: ...6 PWM input mode There are some differences between PWM input mode and normal input capture mode including Two ICx signals are mapped to the same TIx input The two ICx signals are active on edges of...

Page 349: ...the output compare signal to inactive level The values of the TIMx_CCDATx shadow register and the counter still comparing with each other in this mode And the flag still can be set Therefore the inter...

Page 350: ...e sent User can set TIMx_CCMODx OCxPEN to choose capture compare shawdow regisete using capture compare preload registers TIMx_CCDATx or not The time resolution is one count of the counter In one puls...

Page 351: ...output of OCx user need to set the combination of the value of CCxEN The values of TIMx_CNT and TIMx_CCDATx are always compared with each other when the TIM is under PWM mode Only if an update event o...

Page 352: ...gned mode otherwise it will cause unexpected results Here are some example If the value written into the counter is 0 or is the value of TIMx_AR the direction will be updated but the update event will...

Page 353: ...If the compare value in TIMx_CCDATx is greater than the auto reload value the OCxREF will remains 1 Conversely if the compare value is 0 the OCxREF will remains 0 When TIMx_AR 8 the PWM waveforms are...

Page 354: ...configured as output compare mode or PWM mode After selecting one pulse mode the counter will stop counting after the update event UEV is generated Figure 12 20 Example of One pulse mode The followin...

Page 355: ...less of the comparison result OCxFEN fast enable only takes effect when the channel mode is configured for PWM1 and PWM2 modes 12 3 11 Clearing the OCxREF signal on an external event If user set TIMx_...

Page 356: ...x and external trigger synchronization Same as advanced timer See 11 3 16 12 3 14 Timer synchronization All TIMx timers are internally connected to each other This implementation allows any master tim...

Page 357: ...setting TIM2_CTRL1 CNTEN 1 Start TIM1 by setting TIM1_CTRL1 CNTEN 1 Note If user select OCx as the trigger output of TIM1 by configuring MMSEL 1xx OCx rising edge will be used to drive timer2 Master...

Page 358: ...TIM1 In the next example Gated TIM2 with enable signal of TIM1 Setting TIM1 CTRL1 CNTEN 0 to stop TIM1 TIM2 counts on the divided internal clock only when TIM1 is enable Both counters are clocked base...

Page 359: ...le we can use update event as trigger source TIM1 is master TIM2 is slave The configuration steps are shown as below Setting TIM1_CTRL2 MMSEL 010 to use the update event of TIM1 as trigger output Conf...

Page 360: ...as below Setting TIM1 MMSEL 001 to use the enable signal as trigger output Setting TIM1_SMCTRL TSEL 100 to configure the TIM1 to slave mode and receive the trigger input of TI1 Setting TIM1_SMCTRL SM...

Page 361: ...on the edge of TI2 TIMx_SMCTRL SMSEL 010 3 The counter counts on the edges of TI1 and TI2 at the same time TIMx_SMCTRL SMSEL 011 The encoder interface is equivalent to using an external clock with dir...

Page 362: ...ng down Counting up Counting up Counting down Low Counting up Counting down Counting down Counting up Here is an example of an encoder with dual edge triggering selected to suppress input jitter 1 IC1...

Page 363: ...ed as half word 16 bits or one word 32 bits 12 4 1 Register Overview Table 12 2 Register map and reset value Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

Page 364: ...0 01Ch TIMx_CCMOD2 Reserved OC4CEN OC4MD 2 0 OC4PEN OC4FEN CC4SEL 1 0 OC3CEN OC3MD 2 0 OC3PEN OC3FEN CC3SEL 1 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01Ch TIMx_CCMOD2 Reserved IC4F 3 0 IC4PSC 1...

Page 365: ...om IOM signal 1 Select internal CH4 from COMP signal Note For TIM5 setting to 1 is invalid Before operating this bit the extended mode of the chip must be turned on set PWR_CTRL3 EXMODE 13 C3SEL Chann...

Page 366: ...interrupt flag bit is set to 1 when up counting 11 Center aligned mode 3 The counter counts in center aligned mode and the output compare interrupt flag bit is set to 1 when up counting or down counti...

Page 367: ...t or a hardware reset is issued by the slave mode controller the counter and prescaler are reinitialized 0 CNTEN Counter Enable 0 Disable counter 1 Enable counter Note external clock gating mode and e...

Page 368: ...CTRL MSMD bit 010 Update The update event is selected as the trigger output TRGO For example a master timer clock can be used as a slave timer prescaler 011 Compare pulse Triggers the output to send a...

Page 369: ...an be used to reduce the frequency of ETRP 00 Prescaler disable 01 ETRP frequency divided by 2 10 ETRP frequency divided by 4 11 ETRP frequency divided by 8 11 8 EXTF 3 0 External trigger filter These...

Page 370: ...ounter up counting or down counting on the edge of TI1FP1 010 Encoder mode 2 According to the level of TI1FP1 the counter up counting or down counting on the edge of TI2FP2 011 Encoder mode 3 Accordin...

Page 371: ...st enable 0 Disable capture compare 3 DMA request 1 Enable capture compare 3 DMA request 10 CC2DEN Capture Compare 2 DMA request enable 0 Disable capture compare 2 DMA request 1 Enable capture compare...

Page 372: ...g See TIMx_STS CC1OCF description 11 CC3OCF Capture Compare 3 overcapture flag See TIMx_STS CC1OCF description 10 CC2OCF Capture Compare 2 overcapture flags See TIMx_STS CC1OCF description 9 CC1OCF Ca...

Page 373: ...lows in up counting and up down counting modes and underflows in down counting mode When the corresponding channel of CC1 is in input mode This bit is set by hardware when the capture event occurs Thi...

Page 374: ...nd DMA are enabled the corresponding interrupt and DMA will be generated When the corresponding channel of CC1 is in input mode TIMx_CCDAT1 will capture the current counter value and the TIMx_STS CC1I...

Page 375: ...2 0 Output Compare 1 mode These bits are used to manage the output reference signal OC1REF which determines the values of OC1 and OC1N and is valid at high levels while the active levels of OC1 and OC...

Page 376: ...n match on CC1 output Therefore OC is set to the comparison level regardless of the comparison result The delay time for sampling the trigger input and activating the CC1 output is reduced to 3 clock...

Page 377: ...SAMPLING fDTS 32 N 5 1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 3 2 IC1PSC 1 0 Input Capture 1 prescaler These bits are used to select the ratio of the prescaler for IC1 CC1 input When TIMx...

Page 378: ...mode is only active when the internal trigger input is selected by TIMx_SMCTRL TSEL Note CC4SEL is writable only when the channel is off TIMx_CCEN CC4EN 0 7 OC3CEN Output compare 3 clear enable 6 4 OC...

Page 379: ...bits are used to select the input output and input mapping of the channel 00 CC3 channel is configured as output 01 CC3 channel is configured as input IC3 is mapped to TI3 10 CC3 channel is configure...

Page 380: ...ted Capture action occurs when IC1 generates a rising edge When used as external trigger IC1 is non inverted 1 inverted Capture action occurs when IC1 generates a falling edge When used as external tr...

Page 381: ...ler value Counter clock fCK_CNT fCK_PSC PSC 15 0 1 Each time an update event occurs the PSC value is loaded into the active prescaler register 12 4 13 Auto reload register TIMx_AR Offset address 0x2C...

Page 382: ...egister CCDAT1 is only readable When configured as output mode register CCDAT1 is readable and writable 12 4 15 Capture compare register 2 TIMx_CCDAT2 Offset address 0x38 Reset value 0x0000 Bit field...

Page 383: ...de register CCDAT3 is only readable When configured as output mode register CCDAT3 is readable and writable 12 4 17 Capture compare register 4 TIMx_CCDAT4 Offset address 0x40 Reset value 0x0000 Bit fi...

Page 384: ...0 DMA Base Address This bit field defines the first address where the DMA accesses the TIMx_DADDR register When access is done through the TIMx_DADDR first time this bit field specifies the address yo...

Page 385: ...ers TIMx_DCTRL DBADDR 0xD TIMx_CCDAT1 DMA data length half word DMA memory address buffer address in SRAM DMA peripheral address TIMx_DADDR address When an event occurs TIMx will send requests to the...

Page 386: ...onverter DAC The basic timer is directly connected to the DAC inside the chip and drives the DAC directly through the trigger output Main features 16 bit auto reload up counting counters 16 bit progra...

Page 387: ...is generated when the counter reaches the overflow condition and it can be generated by software when TIMx_CTRL1 UPDIS 0 The counter CK_CNT is valid only when the TIMx_CTRL1 CNTEN bit is set The count...

Page 388: ...where you want to clear the counter but do not want to generate an update interrupt Depending on the update request source is configured in TIMx_CTRL1 UPRS When an update event occurs TIMx_STS UDITF...

Page 389: ...13 3 Timing diagram of up counting The internal clock divider factor 2 N CK_PSC CNTEN Timer clock CK_CNT Counter register Counter overflow Update interrupt flag UDITF 0034 0035 Update event UEV 0036 0...

Page 390: ...ck CK_CNT Counter register Update event UEV Update interrupt flag UDITF Write a new value in TIMx_AR 32 31 33 34 35 36 00 01 02 03 FF 36 04 05 06 07 Counter overflow Auto reload preload register Auto...

Page 391: ...T Figure 13 5 Control circuit in normal mode internal clock divided by 1 13 3 4 Debug mode When the microcontroller is in debug mode the Cortex M4 core halted depending on the DBG_CTRL TIMx_STOP confi...

Page 392: ...Reserved MMSEL 2 0 Reserved Reset Value 0 0 0 008h Reserved 00Ch TIMx_DINTEN Reserved UDEN Reserved UIEN Reset Value 0 0 010h TIMx_STS Reserved UDITF Reset Value 0 014h TIMx_EVTGEN Reserved UDGN Reset...

Page 393: ...event sources by software 0 If update interrupt or DMA request is enabled any of the following events will generate an update interrupt or DMA request Counter overflow The TIMx_EVTGEN UDGN bit is set...

Page 394: ...as the trigger output TRGO Sometimes you need to start multiple timers at the same time or enable slave timer for a period of time The counter enable signal is set when TIMx_CTRL1 CNTEN bit is set or...

Page 395: ...1 Reserved Reserved the reset value must be maintained 0 UDITF Update interrupt flag This bit is set by hardware when an update event occurs under the following conditions When TIMx_CTRL1 UPDIS 0 and...

Page 396: ...mer counter will restart and all shadow register will be updated It will restart prescaler counter also 13 4 7 Counter TIMx_CNT Offset address 0x24 Reset value 0x0000 Bit field Name Description 15 0 C...

Page 397: ...oshen Road Hi tech Park North Nanshan District Shenzhen 518057 P R China Bit field Name Description 15 0 AR 15 0 Auto reload value These bits define the value that will be loaded into the actual auto...

Page 398: ...sources of Interrupt Event These include Alarm A Alarm B Wakeup Timer Time Stamp After RTC is enabled by the RCC register and voltage remains in the operating range RTC will not stop timing in any mod...

Page 399: ...g Interrupts events Alarm A Alarm B interrupt event Wakeup interrupt event Timestamp interrupt event RTC function description 14 2 1 RTC block diagram Figure 14 1 RTC Block Diagram RTC includes the fo...

Page 400: ...on is cleared in default so the PWR_CTRL DBKP bit must set to 1 to enable write access to the RTC register Once the backup domain is reset all write protection RTC registers are write protected All wr...

Page 401: ...gister instead User can access the calendar register directly by setting the RTC_CTRL BYPS bit When RTC_CTRL BYPS 0 calendar values are from shadow registers when reading RTC_SUBS RTC_TSH or RTC_DATE...

Page 402: ...ait RTC_INITSTS RSYF bit is set again System reset Calendar complete initialization Calendar complete synchronization 2 Reading calendar value when RTC_CTRL BYPS 1 Reading the calendar value directly...

Page 403: ...s RTC_ALRMxSS RTC_ALARMx Enable Alarm A Alarm B interrupt by set RTC_CTRL ALAIEN RTC_CTRL ALBIEN bit this step can be selected as needed Enable Alarm A Alarm B by setting RTC_CTRL ALAEN RTC_CTRL ALBEN...

Page 404: ...n be enabled by setting RTC_CTRL TSEN bit to 1 When a timestamp event is detected on the RTC_TS pin the calendar values of the event will be stored in the timestamp register RTC_TSSS RTC_TST RTC_TSD a...

Page 405: ...resolution is 0 954 PPM with the range from 487 1 PPM to 488 5 PPM When the input frequency is 32768 Hz calibration period can be configured as 220 RTCCLK cycles or 32 seconds The precision calibratio...

Page 406: ...LK cycles within 16 seconds The calibration period is 8 seconds Using an accurate 8 second period to measure the 1Hz calibration output can ensure that the measurement error is within 1 907ppm 0 5 RTC...

Page 407: ..._PRE Reserved DIVA 6 0 Reserved DIVS 14 0 Reset Value 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 014h RTC_WKUPT Reserved WKUPT 15 0 Reset Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 01Ch RTC_ALARMA MASK4 W...

Page 408: ...Register RTC_TSH Address offset 0x00 Reset value 0x0000 0000 Bit field Name Description 31 23 Reserved Reserved the reset value must be maintained 22 APM AM PM format 0 AM format or 24 hour format 1 P...

Page 409: ...0 Describes the date tens value in BCD format 3 0 DAU 3 0 Describes the date units value in BCD format 14 3 4 RTC Control Register RTC_CTRL Address offset 0x08 Reset value 0x0000 0000 Bit field Name...

Page 410: ...tracts 1 hour to the current time 16 AD1H Add 1 hour summer time change When this bit is set 1 hour can be added to the calendar time This bit is always read as 0 No effect 1 Adds 1 hour to the curren...

Page 411: ...when TSPOL is changed to avoid unwanted RTC_INITSTS TISF setting 2 0 WKUPSEL 2 0 Wakeup clock selection 000 RTC clock is divided by 16 001 RTC clock is divided by 8 010 RTC clock is divided by 4 011...

Page 412: ...cleared by software writing 0 7 INITM Enter Initialization mode 0 Free running mode 1 Enter initialization mode and set calendar time value date value and prescale value 6 INITF Initialization flag R...

Page 413: ...ardware when Alarm B values can be changed after the RTC_CTRL ALBEN bit has been set to 0 0 Alarm B update is not allowed 1 Alarm B update is allowed 0 ALAWF Alarm A write flag This flag is set to 1 b...

Page 414: ...errupt otherwise the changed settings will not take effect immediately but will take effect after the next wakeup In particular when RTC_CTRL WKUPSEL 2 0 is set to 010 the modified setting does not ta...

Page 415: ...seconds mask 0 Seconds match 1 Seconds not match 6 4 SET 2 0 Describes the second tens value in BCD format 3 0 SEU 3 0 Describes the second units value in BCD format 14 3 9 RTC Alarm B Register RTC_...

Page 416: ...value in BCD format 7 MASK1 Alarm seconds mask 0 Seconds match 1 Seconds not match 6 4 SET 2 0 Describes the second tens value in BCD format 3 0 SEU 3 0 Describes the second units value in BCD format...

Page 417: ...t 0x2C Reset value 0x0000 0000 Bit field Name Description 31 SUB1S Add one second 0 No impact 1 Subtract one second to the clock calendar This bit can only be written and read as zero Writing to this...

Page 418: ...value in BCD format 11 8 MIU 3 0 Describes the minute units value in BCD format 7 Reserved Reserved the reset value must be maintained 6 4 SET 2 0 Describes the second tens value in BCD format 3 0 SEU...

Page 419: ...d 15 0 SSE 15 0 Sub second value SSE 15 0 is the value in the synchronous prescaler counter The fraction of a second is provided by the formula below Second fraction RTC_PRE DIVS 14 0 SSE 15 0 RTC_PRE...

Page 420: ...e number of mask pulse out of 220 RTCCLK pulses This effectively decreases the frequency of the calendar with a resolution of 0 9537 ppm 14 3 17 RTC Alarm A sub second register RTC_ ALRMASS Address of...

Page 421: ...ison on sub seconds for Alarm The alarm is set when the seconds unit is incremented assuming that the rest of the fields match 0x1 Only SSV 0 is compared and other bits are not compared 0x2 Only SSV 1...

Page 422: ...tech com Address Nations Tower 109 Baoshen Road Hi tech Park North Nanshan District Shenzhen 518057 P R China Bit field Name Description 31 1 Reserved Reserved the reset value must be maintained 0 TYP...

Page 423: ...ion unit can calculate the identifier of the software when the program is running then compare it with the reference identifier generated during connection and then store it in the specified memory sp...

Page 424: ...orts back to back writes or sequential write read operations CRC_CRC32DAT can be re initialized to 0xFFFFFFFF by setting CRC_CRC32CTRL RESET This operation does not affect the data in register CRC_CRC...

Page 425: ...AT 7 0 Reset Value 0 0 0 0 0 0 0 0 008h CRC32CTRL Reserved RESET Reset Value 0 00Ch CRC16CTRL Reserved CLR ENDHL Reserved Reset Value 0 0 0 010h CRC16DAT Reserved CRC16DAT 7 0 Reset Value 0 0 0 0 0 0...

Page 426: ...te data CRC_CRC32CTRL RESET reset signal will not impact this register Note This register is not a part of CRC calculation and can be used to store any data 15 4 4 CRC32 control register CRC_CRC32CTRL...

Page 427: ...late from MSB or LSB configured endian 0 From MSB to LSB 1 From LSB to MSB This bit is only for data to be verified 0 Reserved Reserved the reset value must be maintained Note 8 bits 16 bits and 32 bi...

Page 428: ...bits 16 bits and 32 bits operations are supported 8 bit operations must be performed twice in a row to ensure that 16 bit initial values are configured properly 15 4 8 LRC result register CRC_LRC Add...

Page 429: ...tions due to software failure The IWDG is best suited for applications that require the watchdog to run as a totally independent process outside the main application but have lower timing accuracy con...

Page 430: ...atically start running after the system is powered on and will generate a system reset unless the software reloads the counter before it reaches 0 16 3 1 Register access protection IWDG_PREDIV and IWD...

Page 431: ...0 this indicates program malfunction IWDG generates reset signal under this circumstance If user wants to configure IWDG pre scale and reload value register it needs to write 0x5555 to IWDG_KEY KEYV 1...

Page 432: ...1x 6 4 26214 4 16 4 2 IWDG configuration flow Software flow 1 Write 0x5555 to IWDG_KEY KEYV 15 0 bits to enable write access of IWDG_PREDIV and IWDG_RELV registers 2 Check IWDG_STS PVU bit or IWDG_STS...

Page 433: ...ed REL 11 0 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 0x0C IWDG_STS Reserved CRVU PVU Reset value 0 0 16 5 2 IWDG key register IWDG_KEY Address offset 0x00 Reset value 0x00000000 Bit field Name Description...

Page 434: ...0x5555 The IWDG_STS PVU bit must be 0 otherwise PD 2 0 value cannot be changed Divide number is as follow 000 divider 4 001 divider 8 010 divider 16 011 divider 32 100 divider 64 101 divider 128 Other...

Page 435: ...eload value from the VDD voltage domain If a write operation is in progress the read back value may be invalid Therefore the read value is valid only when the IWDG_STS CRVU bit is 0 16 5 5 IWDG status...

Page 436: ...wake up interrupt If the watchdog is started and the interrupt is enabled wake up interrupt WWDG_CFG EWINT will be generated when the count value reaches 0x40 Function description If the watchdog is a...

Page 437: ...n analyze the cause of software failure or save important data in the corresponding interrupt service routine ISR and reload the counter to prevent WWDG from resetting Write 0 to the WWDG_STS EWINTF b...

Page 438: ...L WWDG_STOP bit in debug module If this bit is set to 1 the counter stops The counter works normally when the bit is 0 See the chapter on debugging module for details 29 3 2 User interface 17 6 1 WWDG...

Page 439: ...008h WWDG_STS Reserved EWINTF Reset Value 0 17 7 2 WWDG control register WWDG_CTRL Address offset 0x00 Reset value 0x0000007F Bit field Name Description 31 8 Reserved Reserved the reset value must be...

Page 440: ...can be modified as follows 00 CK Counter Clock PCLK1 div 4096 div 1 01 CK Counter Clock PCLK1 div 4096 div 2 10 CK Counter Clock PCLK1 div 4096 div 4 11 CK Counter Clock PCLK1 div 4096 div 8 6 0 W 6...

Page 441: ...with SD I O card specification version 2 0 there are two different data bus modes 1 bit default and 4 bit MMC Fully compatible with Multimedia Card System Specification Version 4 2 and earlier version...

Page 442: ...l operation always consists of a command and response Additionally some operations have a data token There are other operations that include their information directly in the command or response struc...

Page 443: ...esponse SDIO_CMD SDIO_DATA host to devise host to devise device to host command Data block CRC Data block CRC Data block CRC device to host The stop command stops data transfer Single block operation...

Page 444: ...related functions of the MMC SD SD I O card AHB bus interface used to operate the FIFO unit of the register control data transmission in the SDIO adapter module and generate interrupt and DMA request...

Page 445: ...ersions only supports 1 bit data line only SDIO_DAT0 can be used When an SD or SD I O card is connected to the bus SDIO_DAT0 or SDIO_DAT 3 0 can be used by the host to configure data transfers SDIO_CM...

Page 446: ...CTRL PWRCFG bit to turn off SDIO_CLK when the bus is idle When SDIO_CLKCTRL CLKBYP bit is 0 SDIO_CLK is obtained by dividing the frequency of SDIOCLK when SDIO_CLKCTRL CLKBYP bit is 1 SDIO_CLK is dire...

Page 447: ...the card through the SDIO_CMD line one bit of data per SDIO_CLK The 48 bit command contains 1 start bit 1 transmit bit 6 bit command index defined SDIO_CMDCTRL CMDIDX bits 32 bit parameters defined by...

Page 448: ...n SDIO_CMD out Command Unit Idle Pend Wait Send CE ATA command received complete The signal or CPSM is turned off Or command CRC error Response received in CE ATA mode without interruption Wait to ena...

Page 449: ...state the command timer starts to run if a response is received that is the start bit is detected the command state machine CPSM enters the Receive state and when the command state machine CPSM enters...

Page 450: ...t SDIO_STS CMDRUN Command transfer in progress The CRC generator calculates the CRC checksum of all bits preceding the CRC code including start bits transmit bits command index and command parameters...

Page 451: ...r begins after a write to the SDIO_DATCTRL register and setting the SDIO_DATCTRL DATEN bit to 1 When the SDIO_DATCTRL DATDIR bit is 0 the data is from the controller to the card and the DPSM enters th...

Page 452: ...us flag Receive In this state the DPSM receives the card s data and writes it to the data FIFO Depending on the setting of the transfer mode bits in the data control register the data transfer mode ca...

Page 453: ...the DPSM sends data to the card device and then enters the idle state If a FIFO underflow error occurs the DPSM sets the FIFO error flag and enters the idle state Busy In this state the DPSM waits for...

Page 454: ...Table 18 4 Transmit FIFO Status Flags Flag Description SDIO_STS TFIFOF This flag is set high when all 32 transmit FIFO words have valid data SDIO_STS TFIFOE This flag is set high when all 32 transmit...

Page 455: ...rease SDIO_CLK clock frequency 3 Send CMD7 command to select card and configure bus width 4 The configuration process of DMA1 is as follows a Enable DMA1 controller and clear all interrupt flags b Use...

Page 456: ...is is because a card whose internal memory stores the Card Identification Number CID and Card Specific Data CSD can only transmit these information under the condition of data transfer VDD When the SD...

Page 457: ...ard is not compatible it will be placed in an inactive state 4 The SDIO card host broadcasts a CMD2 command ALL_SEND_CID to all active cards All active cards simultaneously send their CID numbers seri...

Page 458: ...ated data length is not aligned with the data block and block misalignment is not allowed parameter WRITE_BLK_MISALIGN for CSD is not set the card will detect block misalignment errors before the star...

Page 459: ...ted in response to the stop transfer command If the host sends the stop transmission command the card has already transmitted the last data block in a certain number of multiple data block operations...

Page 460: ...sfer is controlled by the READ_DAT_UNTIL_STOP CMD11 command This command requires the card to read data from the specified address until the SDIO card host sends a STOP_TRANSMISSION CMD12 command Due...

Page 461: ...estart the erase operation waiting for the first step If a command other than SEND_STATUS and erase command is received the card should set ERASE_RESET in the status register reset the erase sequence...

Page 462: ...s placed in the closed position of the small window the card is not write protected and the user can modify the content in the card There is also a switch on the corresponding part of the slot of the...

Page 463: ...ck in which the command is sent must take into account the lengths of both the old and new passwords 3 On the data line send the CMD42 LOCK UNLOCK command with a suitable data block length and include...

Page 464: ...simultaneously in the same sequence of operations In this case the card host module first sets the password according to the above steps It should be noted that the LOCK_UNLOCK bit should be set in t...

Page 465: ...erform an erase operation on an already unlocked card will cause the operation to fail and set the LOCK_UNLOCK_FAILED error bit in the status register 18 4 11 Card status register Card status register...

Page 466: ...ard unlocked 1 card locked When this bit is set it means the card has been locked A 24 LOCK_UNLOCK_FAILED EX 0 no error 1 error Wrong sequence of commands in lock unlock or wrong password detected C 2...

Page 467: ...ommand results in a change of state this change will be reflected in the response of the next command These four bits are interpreted as decimal numbers 0 to 15 B 8 READY_FOR_DATA SR 0 no ready 1 read...

Page 468: ...re applications The length of the SD state is a 512 bit data block After receiving the ACMD13 command CMD55 then CMD13 the content of the SD status register is transferred to the SDIO card host But it...

Page 469: ...offset value to increase when erasing See below A 399 312 Reserved 311 0 Reserved for Manufacturer The abbreviations in the table for types and clearing condition fields are defined as follows Type E...

Page 470: ...F_PROTECTED_AREA is in bytes SPEED_CLASS These 8 bits indicate the type of speed and a value that can be calculated by calculating PW 2 PW is the write performance Table 18 9 Speed Type Codes SPEED_CL...

Page 471: ...be erased in one operation so that the host can display the progress of the erase operation If this field is 0 the timeout calculation for erasure is not supported Table 18 13 ERASE_SIZE Codes ERASE_...

Page 472: ...interrupt request has been serviced by the MultiMediaCard SD module the interrupt status bits can be cleared by writing the appropriate bits to the SD I O card s internal registers through an I O wri...

Page 473: ...dard interface which is suitable for a variety of application types while taking into account specific users and applications so two types of general commands are defined in the standard application r...

Page 474: ...18 16 Write commands for block based transfers CMD Index Type Parameter Response Format Abbreviation Description CMD23 ac 31 16 0 15 0 Number of blocks R1 SET_BLOCK_COUNT Defines the number of blocks...

Page 475: ...e write protect bit of the specified group CMD30 adtc 31 0 Write Protect Data Addresses R1 SEND_WRITE_PROT If the card is write protected this command requires the card to send the status of the write...

Page 476: ...Index Type Parameter Response Format Abbreviation Description CMD42 adtc 31 0 Stuff bits R1b LOCK_UNLOCK Set clear password or lock unlock card The length of the data block is set by the SET_BLOCKLEN...

Page 477: ...ards and SDIO Cards The CE ATA command is an extension of the MMC V4 2 command so it has the same format The command channel operates in half duplex mode so that commands and responses can be sent and...

Page 478: ...protected except for the R3 response type Each command codeword has an end bit always 1 There are 5 response types and their formats are defined as follows R1 normal response command The code length...

Page 479: ...finition of the level code is the limited voltage window is low and the card is busy Table 18 27 R3 response Bit Width Value Description 47 1 0 Start bit 46 1 0 Transmission bit 45 40 6 111111 Reserve...

Page 480: ...ion Version 1 0 treats the detected CMD5 command as an illegal command and does not respond to it The host that can handle the I O card will send a CMD5 command and if the card returns a response R4 t...

Page 481: ...ntrol function can avoid FIFO underflow transmit mode and overflow receive mode errors The operation process of hardware flow control is to stop SDIO_CLK and freeze the SDIO state machine When the FIF...

Page 482: ...0 0 0 024h SDIO_DTIMER DATTIMEOUT 31 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 028h SDIO_DATLEN Reserved DATLEN 24 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 483: ...state the clock of the card is turned on Note This register cannot be written within 7 HCLK clock cycles after writing data 18 7 3 SDIO clock control register SDIO_CLKCTRL Address offset 0x04 Reset va...

Page 484: ...he PWRCFG bit when the bus is idle 0 SDIO_CLK is always output 1 SDIO_CLK is only output when there is bus activity 8 CLOCKEN Clock enable bit 0 SDIO_CLK is off 1 SDIO_CLK is enabled 7 1 DIV Clock div...

Page 485: ...Bit Field Name Description 31 15 Reserved Reserved the reset value must be maintained 14 CEATAEN CE ATA command If this bit is set CPSM will transmit CMD61 13 INTDIS Not interrupt enable If this bit i...

Page 486: ...SD I O cards can only send short responses the parameters can be changed according to the type of response and the software will distinguish the type of response according to the command sent CE ATA...

Page 487: ...d Card Status 31 1 The highest bit of the card status is always received first and the lowest bit of the SDIO_RESPONSE3 register is always 0 18 7 8 SDIO data timer register SDIO_DTIMER Address offset...

Page 488: ...the value in the data length register must be a multiple of the data block length see SDIO_DATCTRL Before writing to the data control register for data transfer the data timer register and data length...

Page 489: ...lock length 27 128 bytes 1000 block length 28 256 bytes 1001 block length 29 512 bytes 1010 block length 210 1024 bytes 1011 block length 211 2048 bytes 1100 block length 212 4096 bytes 1101 block len...

Page 490: ...rved the reset value must be maintained 24 0 DATCOUNT Data count value When reading this register it returns the number of data bytes to be transmitted Writing this register has no effect Note This re...

Page 491: ...ast 8 more words can be written to the FIFO 13 RXRUN Data receive in progress 12 TXRUN Data transmit in progress 11 CMDRUN Command transfer in progress 10 DATBLKEND Data block sent received CRC check...

Page 492: ...lag 7 CMDSENDC CMDSEND flag clear bit Software sets this bit to clear the SDIO_STS CMDSEND flag 6 CMDRESPRECVC CMDRESPRECV flag clear bit Software sets this bit to clear the SDIO_STS CMDRESPRECV flag...

Page 493: ...eiving FIFO is valid to generate an interrupt 20 TDATVALIDEN Data available in Rx FIFO interrupt enable Setting clearing this bit by software to enable disable the data valid interrupt in the transmit...

Page 494: ...tting command without interrupt 1 Interrupt when command is being transmitted 10 DATBLKENDEN Data block end interrupt enable Setting clearing this bit by software enables disables the end of block tra...

Page 495: ...REN Data CRC fail interrupt enable Setting clearing this bit by software to enable disable the interrupt for block CRC detection failure 0 Data block CRC detection failure does not generate an interru...

Page 496: ...FO Address offset 0x80 Reset value 0x0000 0000 The receive and transmit FIFO is a 32 bit wide read or write set of registers it contains 32 registers on consecutive 32 addresses the CPU can use the FI...

Page 497: ...features Comply with USB2 0 full speed device specification Supports up to 8 configurable USB endpoints Each endpoint supports four transfer types in the USB2 0 protocol Control transfer Bulk transfer...

Page 498: ...used and the endpoint packet buffer size of each endpoint Each endpoint has a buffer description table entry which describes the buffer address size and the number of bytes that need to be transferred...

Page 499: ...ich the user application program on the microcontroller and the USB module accesses the Packet Buffer Memory Figure 19 2 The user applications on the microcontrollers and the USB modules access Packet...

Page 500: ...C host and the USB device the use of bulk transmission allows the PC host to transmit data with maximum efficiency within one frame However when the transmission speed is too fast the USB device will...

Page 501: ...ster As shown in Figure 19 3 when an endpoint uses the double buffer mechanism all four buffer description table entries of the endpoint will be used DATTOG and SW_BUF are responsible for flow control...

Page 502: ...bus is completed the hardware will toggle DATTOG 0 If the application has not finished processing the data in buffer0 corresponding to ADDR3_RX_0 CNT3_RX_0 the software will not toggle SW_BUF SW_BUF 0...

Page 503: ...The process of one time receiving or sending data on the USB is called a transaction and there are three types of transactions Setup transaction Data IN transaction and Data OUT transaction Applicatio...

Page 504: ...he endpoint s sending state to NAK state USB_EPn STS_TX 10 and the hardware sets USB_EPn CTRS_TX bit to generate a correct sending interrupt The software responds to the CTRS_TX interrupt identifies w...

Page 505: ...ket is invalid the USB device sends a PID NAK or STALL handshake packet according to USB_EPn STS_RX Note 1 When the USB device receives data from the host if the size of the received data exceeds the...

Page 506: ...ectly before enabling the Status stage in the OUT direction in addition to setting the Rx direction status of the USB device endpoint to VALID you also need to set STATUS_OUT USB_EPn EP_KIND to 1 indi...

Page 507: ...point is defined as a isochronous endpoint during enumeration the USB host will allocate the required bandwidth for the endpoint in OUT 1 DATA1 SETUP 0 DATA0 Tx STALL Rx VALID USB bus Tx NAK Rx NAK Tx...

Page 508: ...CNTn_RX_1 1 ADDRn_RX_1 CNTn_RX_1 ADDRn_RX_0 CNTn_RX_0 The application initializes the DATTOG bits based on the buffer to be used the first time Each time the transfer is completed USB_EPn CTRS_RX or...

Page 509: ...ated endpoint packet buffer Suspend and resume events 19 4 5 2 1 Suspend events When full speed USB is communicating normally the host will send a PID SOF token packet every millisecond If the USB mod...

Page 510: ...resume event from USB suspend mode 19 4 6 Endpoint initialization 1 Initialize the USB_ADDRn_TX or USB_ADDRn_RX register configure the endpoint Tx or Rx packet buffer start address 2 According to the...

Page 511: ...S_TX 1 0 EPADDR 3 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 010h USB_EP4 Reserved CTRS_RX DATTOG_RX STS_RX 1 0 SETUP EP_TYPE 1 0 EP_KIND CTRS_TX DATTOG_TX STS_TX 1 0 EPADDR 3 0 Reset Value 0 0 0 0...

Page 512: ...e generated Note 1 Software can read and write this bit but only writing 0 is valid and writing 1 is invalid 14 DATTOG_RX Receive data PID toggle bit If the endpoint is not isochronous this bit repres...

Page 513: ...ULK bulk endpoint 01 CONTROL control endpoint 10 ISO isochronous endpoint 11 INTERRUPT interrupt endpoint 8 EP_KIND Endpoint special type EP_TYPE 1 0 EP_KIND meaning 00 BULK DBL_BUF double buffered en...

Page 514: ...int after the transaction is successfully completed 3 0 EPADDR 3 0 Endpoint address This bit indicates the destination endpoint of the communication and must be written before enabling the correspondi...

Page 515: ...B_STS ERROR 1 an interrupt will be generated 12 WKUPM Wake up interrupt enable 0 Disable wake up interrupt 1 Enable wake up interrupt when USB_STS WKUP 1 an interrupt will be generated 11 SUSPDM Suspe...

Page 516: ...set USB_CTRL FSUSPD and then set USB_CTRL LP_MODE 2 LP_MODE Low power mode 0 No effect 1 Enter low power mode in suspend mode Activity on the USB bus wake event resets this bit software can also reset...

Page 517: ...g errors occur 1 No response the host response timed out 2 CRC error CRC check error in data or token packet 3 Bit stuffing error bit stuffing error detected in PID data or CRC 4 Frame format error no...

Page 518: ...s bit but only writing 0 is valid and writing 1 is invalid 2 When the USB module does not receive the PID SOF token packet for 3ms in a row that is 3 ESOF interrupts occur in a row and a SUSPD interru...

Page 519: ...and can detect the occurrence of a resume condition in the suspend state 13 LOCK Lock USB This bit is set by hardware if at least 2 PID SOF token packets are detected continuously after the end of an...

Page 520: ...0x50 Reset value 0x0000 0000 Bit Field Name Description 31 16 Reserved Reserved the reset value must be maintained 15 3 BUFTAB 12 0 Buffer table This bit holds the starting address of the buffer descr...

Page 521: ...eived 0 Since packet buffer memory addresses are word 32 bit aligned this bit must be 0 19 6 2 Send data byte number register n USB_CNTn_TX Address offset USB_ BUFTAB n 16 4 USB local address USB_ BUF...

Page 522: ...The memory block size is 2 bytes 1 The memory block size is 32 bytes 14 10 NUM_BLK 4 0 Number of memory blocks Records the number of memory blocks allocated to the endpoint packet receive buffer and...

Page 523: ...0 BLSIZE 1 00011 6 bytes 128 bytes 01111 30 bytes 512 bytes 10000 32 bytes Reserved 10001 34 bytes Reserved 10010 36 bytes Reserved 11110 60 bytes Reserved 11111 62 bytes Reserved Note 1 The size of t...

Page 524: ...upt control CAN Core Manages the communication between the CAN and the 512 bytes SRAM memory see Figure 20 3 Dual CAN CAN1 and CAN2 each with 512 bytes of SRAM Note USB and CAN1 share a single 512 byt...

Page 525: ...n this CAN controller receive FIFOs and filter mechanism are added as hardware support for CPU message processing and reduce real time response requirement of CAN message Figure 20 1 Topology of CAN n...

Page 526: ...initialization mode the register configuration will not be affected When CAN is in initialization mode message receiving and sending are prohibited and the CANTX pin outputs a recessive bit high leve...

Page 527: ...CAN_MSTS SLPAK bit in response to a sleep or initialization request 20 3 3 Send mailbox Applications can send messages through three sending mailboxes The order of sending three mailbox messages is de...

Page 528: ...tance Filter CAN1 Transmit Mailbox 0 CAN1 Transmit Mailbox 1 CAN1 Transmit Mailbox 2 CAN1 Receive FIFO0 Mailbox 1 Mailbox 2 Mailbox 0 CAN1 Receive FIFO1 Mailbox 1 Mailbox 2 Mailbox 0 CAN1 with 512 byt...

Page 529: ...oid external influence the CAN kernel ignores the acknowledgement error at the moment of acknowledgement bit of data remote frame it does not detect whether there is an dominant bit To enter loopback...

Page 530: ...CANRX pin is disconnected from the CAN bus while the CANTX pin is driven to the recessive bit state It can be used for Run time self diagnose just like CAN can be tested in loop back mode but not affe...

Page 531: ...ority Changing to the Ready status once the mailbox becomes the highest priority mailbox The messages in the ready mailbox is sent as soon as the CAN bus enters the idle state then enter the sending s...

Page 532: ...red communication mode The internal timer of CAN is activated in time triggered communication mode It is incremented at each CAN bit time see 20 4 7 Section CAN samples the value of the internal timer...

Page 533: ...e in the FIFO FIFO is completely managed by hardware which can simplify the application program ensure the consistency of data and reduce the processing time of CPU Valid message According to CAN prot...

Page 534: ...way the latest received message will not be discarded If the FIFO lock function is enabled set the CAN_MCTRL RFLM bit then the newly received messages will be discarded and the software can read the f...

Page 535: ...s to meet this demand These filter banks are used to receive only those messages needed by software Each filter bank x contains two 32 bit registers namely CAN_FxR0 and CAN_FxR1 Setting of filter bit...

Page 536: ...red Identifier list mode 32 bit Mask Mode CAN_FS1 FSCx 1 CAN_FM1 FBx 0 FBC 31 21 FBC 20 3 STDID 10 0 EXTID 28 18 EXTID 17 0 IDE RTR 0 filter ID filter Mask USER ID FBC2 FBC1 FBC0 FBC 31 21 FBC2 FBC2 F...

Page 537: ...register This filter matching index can help to identify which types of message it is in this receive FIFO The filter matching sequence number can be used two ways The first one is comparing the filt...

Page 538: ...ilter rules of CAN When receiving a message its identifier is first compared with the filter configured in identifier list mode If there is a match the message will be stored in the associated FIFO an...

Page 539: ...ge To avoid programming errors in software setting the bit time characteristic register CAN_BTIM can only be done when CAN is initialized Its operation can be simply understood as dividing each nomina...

Page 540: ...bit when CAN itself does not send the recessive bit Note 1 The time characteristics and resynchronization mechanism of CAN bits are detailed in the ISO11898 standard 2 In order to improve the CAN bit...

Page 541: ...Data Field 8 Nbit CRC Field 16bit 2bit 7bit Inter Frame Space Inter Frame Space or Overload Frame ID 28 18 DLC CRC EOF ID 17 0 SOF RTR r1 r0 ACK SRR IDE Arbitration Field 32bit Ctrl Field 6bit Data N...

Page 542: ..._RFF0 FFMP0 bit is not 00 When FIFO0 becomes full and the CAN_ RFF0 FFULL0 bit is set When FIFO0 overruns and the CAN_ RFF0 FFOVR0 bit is set FIFO1 interrupt CAN_RX1_IRQn FIFO1 receive a new message a...

Page 543: ...tus What s more by setting the CAN_INTE register such as CAN_INTE LECITE bit the software can flexibly control the generation of interrupts when an error is detected 20 5 2 Bus Off recovery When TXEC...

Page 544: ...fly but its advised not to do so Otherwise during few cycles CAN behavior will become unpredictable 8 Exit Initialization mode by clearing CAN_MCTRL INIRQ bit 9 Wait for CAN_MSTS INIAK bit become 0 ex...

Page 545: ...trol and status registers By configuring these registers user can configure CAN parameters such as working mode and baud rate start message sending handling message reception interrupt setting read di...

Page 546: ...Reserved RFFOM1 FFOVR1 FFULL1 Reserved FFMP1 1 0 Reset Value 0 0 0 0 0 014h CAN_INTE Reserved SLKITE WKUITE ERRITE Reserved LECITE BOFITE EPVITE EWGITE Reserved FOVITE1 FFITE1 FMPITE1 FOVITE0 FFITE0...

Page 547: ...x 1A8h CAN_TMDL2 DATA3 7 0 DATA2 7 0 DATA1 7 0 DATA0 7 0 Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 1ACh CAN_TMDH2 DATA7 7 0 DATA6 7 0 DATA5 7 0 DATA4 7 0 Reset Value...

Page 548: ...0 0 0 0 0 0 0 0 0 0 0 0 0 208h Reserved 20Ch CAN_FS1 Reserved FSC 13 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 210h Reserved 214h CAN_FFA1 Reserved FAF 13 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 218...

Page 549: ...shan District Shenzhen 518057 P R China Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2A8h CAN_F13B1 FBC 31 0 Reset Value x x x x x x x x x x x...

Page 550: ...eset CAN after which CAN enters sleep mode and CAN_RFFx FFMP bit and CAN_MCTRL register are initialized to their reset values After that the hardware automatically clears this bit 14 8 Reserved Reserv...

Page 551: ...the next received message will be discarded 2 TXFP Transmit FIFO priority When there are multiple messages waiting to be sent at the same time this bit determines the sending order of these messages...

Page 552: ...n CAN_INTE SLKITE 1 once CAN enters sleep mode hardware will set this bit and then the corresponding interrupt will be triggered When this bit is set if the CAN_INTE SLKITE bit is set a state change i...

Page 553: ...is bit is the confirmation of the software request to enter the initialization mode the CAN_MCTRL INIRQ bit is set Hardware clears this bit when CAN exits initialization mode CAN leaves Initialization...

Page 554: ...ls to send due to the loss of arbitration set this bit 17 TXOKM2 Transmission OK of mailbox 2 The hardware updates this bit after each sending attempt of mailbox 2 0 The last sending attempt is not ye...

Page 555: ...s this bit when the sending message of mailbox 0 is idle If there is no message waiting to be sent in mailbox 0 it will have no effect to set this bit 6 4 Reserved Reserved the reset value must be mai...

Page 556: ...en FIFO 0 is full a new message is received and the message meets the filtering conditions the hardware sets this bit This bit is cleared by software 3 FFULL0 FIFO 0 full When there are 3 messages in...

Page 557: ...reset value must be maintained 1 0 FFMP1 1 0 FIFO 1 message pending Number of messages in FIFO 1 These two bits reflect the number of messages stored in the current receiving FIFO 1 Every time a new m...

Page 558: ...1 overflow interrupt enable 0 When CAN_RFF1 FFOVR bit is set no interrupt is generated 1 When CAN_RFF1 FFOVR bit is set an interrupt is generated 5 FFITE1 FIFO 1 full interrupt enable 0 When CAN_RFF1...

Page 559: ...Reserved Reserved the reset value must be maintained 6 4 LEC 2 0 The Last error code When an error is detected on the CAN bus the hardware is set according to the error situation When the message is...

Page 560: ...de is prohibited 1 Loopback mode is allowed 29 26 Reserved Reserved the reset value must be maintained 25 24 RSJW 1 0 Resynchronization jump width For resynchronization this bit field defines the uppe...

Page 561: ...it Field Name Description 31 21 STDID 10 0 EXTID 28 18 Standard identifier or extended identifier Depending on the content of CAN_TMIx IDE bits these bits are either standard identifiers or high bytes...

Page 562: ...stamp CAN_TMDTx MTIM 15 0 is the last two bytes sent CAN_TMDTx MTIM 7 0 is the seventh byte and CAN_TMDTx MTIM 15 8 is the eighth byte They replace the data written in CAN_TMDHx 31 16 CAN_TMDLx DATA6...

Page 563: ...he mailbox is not empty all bits in this register are write protected Address offset 0x18c 0x19c 0x1ac Reset value undefined Bit Field Name Description 31 24 DATA7 7 0 Data byte 7 Data byte 7 of the m...

Page 564: ...eserved Reserved the reset value must be maintained Receive FIFO mailbox data length and time stamp register CAN_RMDTx x 0 1 Address offset 0x1B4 0x1C4 Reset value undefined Notes All receiving mailbo...

Page 565: ...DATA1 7 0 Data byte 1 Data byte 1 of the message 7 0 DATA0 7 0 Data byte 0 Data byte 0 of the message Notes the message contains 0 to 8 bytes of data starting from byte 0 Receive FIFO mailbox high byt...

Page 566: ...Filter init mode Initialization mode settings for all filter groups 0 The filter group works in normal mode 1 The filter group works in initialization mode CAN filter mode register CAN_FM1 Address off...

Page 567: ...x 13 0 0 The filter bit width is 2 16 bits 1 The filter bit width is a single 32 bit CAN filter FIFO assignment register CAN_FFA1 Address offset 0x214 Reset value 0x0000 0000 Notes You can only write...

Page 568: ...wo 32 bit registers CAN_FiR 2 1 Only when the corresponding CAN_FA1 FACx bit is cleared or the CAN_FMC FINIT bit is set the corresponding filter register can be modified Bit Field Name Description 31...

Page 569: ...shan District Shenzhen 518057 P R China bank are different For the mapping of filters function description and association of mask registers see 20 4 5 Section identifier filtering Mask identifier reg...

Page 570: ...nment standard and PCM standard Both of them are synchronous serial interface communication protocols Main features 21 2 1 SPI features Full duplex mode and simplex synchronous mode Support master mod...

Page 571: ...ave input pin Data is send by the MOSI pin of master device and received from the MOSI pin of slave device NSS chip select pin There are two types of NSS pin internal pin and external pin If the inter...

Page 572: ...el and the slave should connect NSS pin to the low level during the entire data frame transfer NSS output mode NSS output of the master device is enable SPI_CTRL1 MSEL 1 SPI_CTRL2 SSOEN 1 SPI as the m...

Page 573: ...apture by setting SPI_CTRL1 CLKPOL bit and SPI_CTRL1 CLKPHA bit When CLKPOL 0 CLKPHA 0 the SCLK pin will keep low in idle state and the data will be sampled at the first edge which is rising edge When...

Page 574: ...er the first data is written to the SPI_DAT register the transmission will start When the first bit of the data is sent the data bytes are loaded from the data register into the shift register in para...

Page 575: ...PI_STS TE flag Figure 21 5 Schematic diagram of the change of TE RNE BUSY when the host is continuously transmitting in full duplex mode Master two wire one way send only mode SPI_CTRL1 MSEL 1 SPI_CTR...

Page 576: ...as follows Enable the receive only mode SPI_CTRL1 RONLY 1 Enable SPI module set SPI_CTRL1 SPIEN 1 in master mode SCLK clock signal is generated immediately and serial data is continuously received be...

Page 577: ...TRL1 BIDIRMODE 1 SPI_CTRL1 BIDIROEN 0 SPI_CTRL1 RONLY 0 When SPI_CTRL1 SPIEN 1 the receiving process starts There is no data output in this mode the received data bits are sequentially and serially sh...

Page 578: ...llel b0 b2 b1 b3 b4 b6 b5 b0 b7 b1 b2 b3 b5 b4 b6 b7 b1 b0 b3 b2 b4 b5 b7 b6 DATA1 0x11 DATA2 0x22 DATA3 0x33 b0 b2 b1 b3 b4 b6 b5 b0 b7 b1 b2 b3 b5 b4 b6 b7 b1 b0 b3 b2 b4 b5 b7 b6 DATA1 0xAA DATA2 0...

Page 579: ...LSBFF bit to define the frame format 5 Configure the NSS mode as described above for the NSS function 6 Run mode is configured by SPI_CTRL1 MSEL bit SPI_CTRL1 BIDIRMODE bit SPI_CTRL1 BIDIROEN bit and...

Page 580: ...lag SPI_STS BUSY is always high In slave mode the continuity of communication is determined by the SPI master device However even if the communication is continuous the BUSY flag SPI_STS BUSY will be...

Page 581: ...4 Disabling the SPI In order to turn off the SPI module different operation modes require different operation steps Master or slave full duplex mode 1 Wait for the RNE flag SPI_STS RNE to be set to 1...

Page 582: ...the SPI needs to be enabled SPI_CTRL2 TDMAEN 1 When the SPI is only used for receiving data only the receive DMA channel of the SPI needs to be enabled SPI_CTRL2 RDMAEN 1 In send mode after DMA has s...

Page 583: ...o 1 an interrupt will be generated In order to keep the synchronization of the next CRC calculation result of the master slave device the user should clear the CRC value of the master slave device Set...

Page 584: ...SPI_STS MODERR bit may be set to 1 In this case the SPI_STS MODERR bit indicates that there is a multi master collision The interrupt routine can perform a reset or return to the default state to rec...

Page 585: ...is sent SD Serial data shared with MOSI pin used for data send and receive WS Channel selection shared with NSS pin used as data control signal output in master mode and used as input in slave mode M...

Page 586: ...be transmitted and set the data bit width of the channel by setting the SPI_I2SCFG CHBITS bits There are 4 data formats for sending data as follows 16 bit data is packed into 16 bit data frame 16 bit...

Page 587: ...mission For example if the user sends 24 bit data 0x95AA66 the CPU will first write 0x95AA into the SPI_DAT register and then write 0x66XX into the SPI_DAT register only the upper 8 bit data is valid...

Page 588: ...rresponding interrupt The sending is performed by hardware even if the last 16 bits 0x0000 are not sent the hardware will set the TE SPI_STS TE bit to 1 and the corresponding interrupt will be generat...

Page 589: ...l precision CLKPOL 0 Figure 21 18 MSB aligns 24 bit data CLKPOL 0 Figure 21 19 MSB aligned 16 bit data is extended to 32 bit packet frame CLKPOL 0 CLK WS SD Left channel 16 bit or 32 bit Right Channel...

Page 590: ...d or write the SPI_DAT register twice during each frame of data transmission For example if the user sends 24 bit data 0x95AA66 the CPU will first write 0xXX95 only the lower 8 bit data is valid the u...

Page 591: ...SPI_DAT register first once the valid data starts to be send the next TE SPI_STS TE event will be generated In the process of receiving data once the device receives valid data the RNE SPI_STS RNE ev...

Page 592: ...na Figure 21 23 PCM standard waveform 16 bits Figure 21 24 PCM standard waveform 16 bit extended to 32 bit packet frame 21 4 2 Clock generator In the master mode the linear divider needs to be set cor...

Page 593: ...gure 21 26 Audio sampling frequency definition The sampling signal frequency of the audio can be set by setting the SPI_I2SPREDIV ODD_EVEN bit and the SPI_I2SPREDIV LDIV 7 0 bits Audio can be sampled...

Page 594: ...71 0 45 0 45 21 4 3 I2 S Transmission and reception sequence I2S initialization sequence 1 The user can set the SPI_I2SPREDIV LDIV 7 0 bits and SPI_I2SPREDIV ODD_EVEN bit to configure the related pres...

Page 595: ...vice is enabled and the data has been written to the I2S data register the external master device can start communication When the first clock edge representing the next data transfer arrives the new...

Page 596: ...CFG I2SEN 0 Slave mode The receiving process of the slave mode is similar to that of the master mode with the following differences The CHSIDE flag SPI_STS CHSIDE indicates which channel corresponds t...

Page 597: ...register has 2 error flag bits Overflow flag OVER When the RNE flag SPI_STS RNE is set to 1 but there is still data sent to the receive buffer an overflow error will occur At this time the OVER flag S...

Page 598: ...USY OVER MODERR CRCERR UNDER CHSIDE TE RNE Reset Value 0 0 0 0 0 0 1 0 00Ch SPI_DAT Reserved DAT 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 010h SPI_CRCPOLY Reserved CRCPOLY 15 0 Reset Value 0 0...

Page 599: ...s bit should be set immediately after the last data is written in SPI_DAT register Note Not used in I2 S mode 11 DATFF Data frame format 0 8 bit data frame format is used for sending receiving 1 16 bi...

Page 600: ...e When turning off the SPI device please follow paragraph 21 3 4 Section s procedure operation 5 3 BR 2 0 Baud rate control 000 fPCLK 2 001 fPCLK 4 010 fPCLK 8 011 fPCLK 16 100 fPCLK 32 101 fPCLK 64 1...

Page 601: ...error SPI_STS CRCERR SPI_STS OVER SPI_STS UNDER SPI_STS MODERR is generated this bit controls whether an interrupt is generated 0 Disable error interrupt 1 Enable error interrupt 4 3 Reserved Reserve...

Page 602: ...and cleared according to the sequence of software operations For more information about software sequences refer to 21 3 7 for details Note Not used in I2 S mode 4 CRCERR CRC error flag 0 The received...

Page 603: ...ta sending and receiving can be 8 bit or 16 bit To ensure correct operation the data frame format needs to be determined before enabling the SPI For 8 bit data the buffer is 8 bit and only SPI_DAT 7 0...

Page 604: ...ing this register when the BUSY flag SPI_STS BUSY is 1 may read incorrect values Note not used in I2 s mode 21 5 8 SPI TX CRC register SPI_CRCTDAT Address offset 0x18 Reset value 0x0000 Bit field Name...

Page 605: ...M frame synchronization 0 Short frame synchronization 1 Long frame synchronization Note This bit is only meaningful when SPI_I2SCFG STDSEL 11 used by the PCM standard Note not used in SPI mode 6 Reser...

Page 606: ...ister SPI_I2SPREDIV Address 0x20 Reset value 0x0002 Bit field Name Description 15 10 Reserved Reserved the reset value must be maintained 9 MCLKOEN Master clock output enable 0 Disable master clock ou...

Page 607: ...ter Supports 7 bit 10 bit address mode and broadcast addressing As I2C master it can generate clock start and stop signal As I2C slave it supports address detection stop bit detection function Support...

Page 608: ...BSF 1 the I2C interface keeps the clock line low after receiving the data byte waiting for the software to read STS1 and then read the data register buffer and shift register are full If clock extend...

Page 609: ...stop bit The start and stop conditions are generated by software in the master mode Start bit is a level conversion from high to low on SDA line when SCL is high Stop bit is a level transition from l...

Page 610: ...clock is still in the low period the low to high switch of this clock will not change the state of the SCL line Therefore the SCL line is kept low by the device with the longest low level period A dev...

Page 611: ...I2C_STS2 TRF indicates whether it is currently in receiver mode or transmission mode When sending data to I2C bus in transmission mode the software should follow the following steps 1 First enable I2C...

Page 612: ...ster is empty write DAT 3 EV3 I2C_STS1 TXDATE 1 shift register is not empty data register is empty write DAT will clear the event 4 EV3 2 I2C_STS1 ACKFAIL 1 ACKFAIL bit of STS1 register write 0 to cle...

Page 613: ...detects the STOP bit on I2C bus set I2C_STS1 STOPF to 1 and if the I2C_CTRL2 EVTINTEN bit is set an interrupt will be generated The software clears the I2C_STS1 STOPF bit by reading the I2C_STS1 regis...

Page 614: ...header byte 11110xx0 and then sends the lower 8 bits of the slave address where xx represents the highest 2 bits of the 10 bit address In the 7 bit address mode only one address byte needs to be sent...

Page 615: ...DAT register will clear the event 5 EV8_2 I2C_STS1 TXDATE 1 I2C_STS1 BSF 1 request to set stop bit These two events are cleared by the hardware when a stop condition is generated 6 EV9 I2C_STS1 ADDR1...

Page 616: ...is set to 1 by hardware and if the I2C_CTRL2 EVTINTEN bit is set to 1 an interrupt will be generated Then the master device waits to read the STS1 register once and then reads the STS2 register Note I...

Page 617: ...Instructions 1 EV5 I2C_STS1 STARTBF 1 reading STS1 and then writing the address into the DAT register will clear this event 2 EV6 I2C_STS1 ADDRF 1 reading STS1 and STS2 in sequence will clear this ev...

Page 618: ...ned by software whether suspend I2C device as slave when data is discarded in transmission and the bus releases by hardware it will have two situation If an error start condition is detected the slave...

Page 619: ...in the interrupt handler after the DMA transfer is completed if interrupt enable Note When I2C and other peripherals use the same DMA controller they cannot be turned on at the same time Transmit pro...

Page 620: ...can improve the reliability of communication The CRC 8 polynomial uses by the PEC calculator is C x x8 x2 x 1 In transmit mode software sets I2C_CTRL1 PEC transfer bit in the last I2C_STS1 TXDATE even...

Page 621: ...rities between SMBus and I2C Both bus protocols contain of 2 wires a clock wire SCL and a data wire SDA with an optional SMBus alert wire The data format is similar SMBus data format is similar to 7 b...

Page 622: ...device This is the reason why SMBus has a minimum transmission rate limitation to prevent the bus from locking up for a long time after the timeout occurs I2C bus is essentially a DC bus that is to s...

Page 623: ...RL1 SMBTYPE 1 use the SMB master header field 2 In order to support ARP I2C_CTRL1 ARPEN 1 in SMBus host mode I2C_CTRL1 SMBTYPE 1 software needs to respond to the I2C_STS2 SMBHADDR bit in SMBus slave m...

Page 624: ...h I2C_CTRL1 Reserved SWRESET Reserved SMBALERT PEC ACKPOS ACKEN STOPGEN STARTGEN NOEXTEND GCEN PECEN ARPEN SMBTYPE Reserved SMBMODE EN Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 004h I2C_CTRL2 Reserved D...

Page 625: ...software It will be cleared by hardware when PEC has been transferred or by start or stop condition or when I2C_CTRL1 EN 0 0 No PEC transfer 1 PEC transfer Note When arbitration is lost the calculati...

Page 626: ...RL1 until this bit is cleared by hardware Otherwise the STOPGEN STARTGEN or PEC bits may be set twice 8 STARTGEN Start generation It can be set or cleared by software Or it will be cleared by hardware...

Page 627: ...eset value must be maintained 12 DMALAST DMA last transfer 0 Next DMA EOT is not the last transfer 1 Next DMA EOT is the last transfer Note This bit is used in the master receiving mode so that a NACK...

Page 628: ...ned 5 0 CLKFREQ 5 0 I2C Peripheral clock frequency CLKFREQ 5 0 should be the APB clock frequency to generate the correct timming 000000 Disable 000001 Disable 000010 2MHz 000011 3MHz 100100 36MHz 1001...

Page 629: ...g mode enable 0 Disable dual address mode only OADDR1 is recognized 1 Enable dual address mode both OADDR1 and OADDR2 are recognized Note Valid only for 7 bit address mode 22 6 6 I2C Data register I2C...

Page 630: ...ve mode slave device resets the communication and hardware frees the bus Timeout in master mode hardware sends the stop condition 13 Reserved Reserved the reset value must be maintained 12 PECERR PEC...

Page 631: ...cleared by hardware when I2C_CTRL1 EN 0 0 Data register is not empty 1 Data register is empty When sending data this bit is set to 1 when the data register is empty and it is not set at the address se...

Page 632: ...the data register has not been read I2C_STS1 RXDATNE 1 In sending mode when a new data is to be transmitted and the data register has not been written with the new data I2C_STS1 TXDATE 1 Note After re...

Page 633: ...en I2C_CTRL1 EN 0 0 SMBus host address was not received 1 when I2C_CTRL1 SMBTYPE 1 and I2C_CTRL1 ARPEN 1 SMBus host address is received 5 SMBDADDR SMBus device default address Slave mode Hardware clea...

Page 634: ...In slave mode 1 In master mode When the interface is in the master mode I2C_STS1 STARTBF 1 the hardware sets this bit 22 6 9 I2C Clock control register I2C_CLKCTRL Address offset 0x1c Reset value 0x00...

Page 635: ...e the definitions of these parameters in the data sheet for details 4 These delays have no filters 22 6 10 I2C Rise time register I2C_TMRISE Address offset 0x20 Reset value 0x0002 Note The I2C_TMRISE...

Page 636: ...on Baud rate generator the highest baud rate can reach 4 5Mbit s Support serial data frame structure with 8 or 9 data bits 1 or 2 stop bits Generation and checking of supported parity bits Support har...

Page 637: ...ter is active and not sending data the TX pin is pulled high When the transmitter is inactive the TX pin reverts to the I O port configuration RX is an input pin for serial data reception data is reco...

Page 638: ...quired The CK pin is used for clock output for synchronous transfers Clock phase and polarity are software programmable During the start and stop bits the CK pin does not output clock pulses The CK pi...

Page 639: ...o the configuration of the data bit length with the least significant bit first If USART_CTRL1 TXEN is reset during a data transfer it will cause the baud rate counter to stop counting and the data be...

Page 640: ...nsmitter process 1 Enable USART_CTRL1 UEN to activate USART 2 Configure the transmitter s baud rate data bit length parity bit optional the number of stop bits or DMA configuration 3 Activate the tran...

Page 641: ...ift register is sending data the data is stored in the TDR register and after the current transmission is completed the data is put into the shift register When a frame containing data is sent and USA...

Page 642: ...four requirements the USART receiver thinks that it has not received the correct start bit and will exit the start bit detection and Return to idle state and wait for falling edge Figure 23 6 Start b...

Page 643: ...irst shifted from the RX pin into the receive shift register 5 When the data of the received shift register is moved to the RDR register USART_STS RXDNE is set and the data can be read out If USART_CT...

Page 644: ...irst then write USART_DAT register During single byte communication no noise interrupt generated because it occurs with USART_STS RXDNE and the hardware will generate an interrupt when the USART_STS R...

Page 645: ...8 then DIV_Decimal 16 0 98 15 68 Nearest integer DIV_Decimal 16 0x10 out of configurable range so a carry to integer is required So DIV_Integer 20 1 21 0x15 DIV_Decimal 0x0 So USART_BRCF 0x150 Example...

Page 646: ...ansceiver and the high to low transition timing of the transceiver these factors will affect the overall clock system variation Only when the sum of the above four changes is less than the tolerance o...

Page 647: ...e receiver calculates the number of 1s in the data again If it is an odd number the check is passed indicating that no errors occurred during the transmission process If it is not an odd number it mea...

Page 648: ...dress will be the source address of the data transfer 2 Set the address of the data memory When a data transfer request occurs the transferred data will be written to this address 3 Set the amount of...

Page 649: ...1 23 4 8 Hardware flow control USART supports hardware flow control The purpose is to coordinate the sending and receiving parties so that the data will not be lost The connection method is shown in t...

Page 650: ...RT_CTRL3 CTSEN to enable CTS CTS is an input signal used to judge whether data can be sent to the other device The low level is valid and the low level indicates that the device can send data to the o...

Page 651: ...to be communicated when needed so that the slave device is in an active state and transmits data with the master device The USART can wake up from mute mode by idle line detection or address mark det...

Page 652: ...be written to 1 by software and USART enters mute mode Note When the receive buffer contains no data RXNE 0 in USART_SR the USART_CTRL1 RCVWU bit can be written to 0 or 1 Otherwise the write operation...

Page 653: ...CLKPOL 1 the default level of CLK is high When the phase polarity is 0 USART_CTRL2 CLKPHA 0 the data is sampled on the first edge of the clock when the phase polarity is 1 USART_CTRL2 CLKPHA 1 the dat...

Page 654: ...mode Data is sampled on CK without any oversampling But setup time and hold time depending on baud rate 1 16 bit time must be considered Figure 23 14 USART synchronous transmission example Figure 23...

Page 655: ...Single wire half duplex mode USART supports single wire half duplex communication allowing data to be transmitted in both directions but only allows data to be transmitted in one direction at the sam...

Page 656: ...infrared light pulse to represent a logic 0 and the pulse width is specified as 3 16 of a bit period in normal mode as shown in the Figure 23 19 USART only supports up to 115200bps for SIR ENDEC The...

Page 657: ...LINMEN bit Note When using LIN mode USART_CTRL2 STPB 1 0 USART_CTRL2 CLKEN USART_CTRL3 SCMEN USART_CTRL3 HDMEN USART_CTRL3 IRDAMEN these bits should be kept clear LIN transmitting When LIN is sent th...

Page 658: ...the start bit the circuit samples each subsequent bit at the 8th 9th and 10th oversampling clock points of each bit When 10 or 11 consecutive bits are detected as 0 and followed by a delimiter it mean...

Page 659: ...just long enough break detected Case 3 break signal long enough break detected RX line Sample Break frame Sample data Break frame Idle Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit7 Bit5 Bit6 Bit8 Bit9 Bit10 0 0...

Page 660: ...stop bits can be used when sending data So 1 5 stop bits are recommended as this avoids configuration transitions In smart card mode the data bits should be configured as 8 bits and the parity bit sh...

Page 661: ...clock The smart card mode is delayed by a minimum of 1 2 baud clock than normal operation In normal operation USART_STS TXC is set when a frame containing data is sent and USART_STS TXDE 1 In smart ca...

Page 662: ...one interrupt request can be generated at the same time Table 23 7 USART interrupt request Interrupt function Interrupt event Event flag Enable bit USART global interrupt Transmission data register is...

Page 663: ...Y Y Y Y Y Y Y Synchronous mode Y Y Y N N N N Single wire half duplex mode Y Y Y Y Y Y Y Smartcard mode Y Y Y N N N N IrDA infrared mode Y Y Y Y Y Y Y DMA communication mode Y Y Y Y Y Y Y Hardware flo...

Page 664: ...0 0 0 0 0 0 018h USART_GTP Reserved GTV 7 0 PSCV 7 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 7 2 USART Status register USART_STS Address offset 0x00 Reset value 0x0000 00C0 Bit field Name Descr...

Page 665: ...er 0 The read data buffer is empty 1 The read data buffer is not empty 4 IDLEF IDLE line detected flag Within one frame time the idle state is detected at the RX pin and this bit is set to 1 When USAR...

Page 666: ...mitted data has both framing errors and overload errors the hardware will continue to transmit the data and only set the USART_STS OREF flag bit In the multi buffer communication mode if the USART_CTR...

Page 667: ...RXEN are disabled respectively Bit field Name Description 31 16 Reserved Reserved the reset value must be maintained 15 4 DIV_Integer 11 0 Integer part of baud rate divider 3 0 DIV_Decimal 3 0 Fracti...

Page 668: ...erated when USART_STS TXDE bit is set 0 Send buffer empty interrupt is disabled 1 Send buffer empty interrupt is enabled 6 TXCIEN Transmit complete interrupt enable If this bit is set to 1 an interrup...

Page 669: ...receiver is in mute mode 0 SDBRK Send Break Character The software transmits a break character by setting this bit to 1 This bit is cleared by hardware during stop bit of the break frame transmission...

Page 670: ...7 Reserved Reserved the reset value must be maintained 6 LINBDIEN LIN break detection interrupt enable If this bit is set to 1 an interrupt will be generated when USART_STS LINBDF bit is set 0 Discon...

Page 671: ...is bit is used to enable RTS hardware flow control function 0 RTS hardware flow control is disabled 1 RTS hardware flow control is enabled Note This bit cannot be used for UART4 5 6 7 7 DMATXEN DMA tr...

Page 672: ...bled 1 Error interrupt enabled 23 7 8 USART guard time and prescaler register USART_GTP Address offset 0x18 Reset value 0x0000 0000 Bit field Name Description 31 16 Reserved Reserved the reset value m...

Page 673: ...t to 00000001 In Smartcard mode PSCV 7 5 is reserved PSCV 4 0 is used to set the frequency division factor of the peripheral clock APB1 APB2 to generate the smart card clock The actual frequency divis...

Page 674: ...PI mode In Single mode it supports standard SPI operation and can work in half duplex and full duplex modes Support indirect mode and memory mapped mode 8 bit 16 bit 32 bit data access mode support Su...

Page 675: ...ates with peripherals through commands Each command includes five phase Instruction phase Address phase Mode bits phase Wait cycles phase and Data phase Any phase can be skipped but at least remains o...

Page 676: ...in Single SPI mode QSPI_CTRL0 SPI_FRF 1 0 00 When QSPI_CTRL0 TMOD 1 0 01 the QSPI is in indirect transmission mode and the byte to be transmitted is sent to the flash memory during the data transmissi...

Page 677: ...ress can occupy multiple FIFO locations Both instructions and addresses must be programmed in the QSPI_DATx registers The write operation can be divided into three phase the Instruction phase the Addr...

Page 678: ...timing in CTRL0 SPI_FRF specified mode QSPI_ENH_CTRL0 TRANS_TYPE 1 0 shall be configured as 0x02 When QSPI_CTRL0 SPI_FRF 1 0 is configured as 0x02 Quad mode N 3 when QSPI_CTRL0 SPI_FRF 1 0 is configu...

Page 679: ...ration Timing In quad mode N 3 each read command data will be transmitted in the format configured by QSPI_CTRL0 SPI_FRF 1 0 Configured as 0x2 for quad mode Both address and instruction receive timing...

Page 680: ...SPI_CTRL0 SPI_FRF 1 0 is configured as 0x01 Dual mode N 1 Instruction and address are received timing in QSPI_CTRL0 SPI_FRF specified mode The QSPI_ENH_CTRL0 TRANS_TYPE 1 0 configuration should be 0x2...

Page 681: ...22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000h QSPI_CTRL0 Reserved SPI_FRF 1 0 Reserved CFS 3 0 Reserved SSTE SRL Reserved TMOD 1 0 SCPOL SCPH FRF 1 0 Reserved DFS 4 0 Reset Value 1...

Page 682: ...set Value 0 0 0 0 0 0 0 034h QSPI_RISTS Reserved XRXORI S MMCRIS RXFFRIS RXFORIS RXFURIS TXFORIS TXFERIS Reset Value 0 0 0 0 0 0 0 038h QSPI_TXFOI_CL R Reserved TXFOIC Reset Value 0 03Ch QSPI_RXFOI_CL...

Page 683: ...0 0 0 0 0 0 0 100h QSPI_XIP_INCR_ TOC Reserved ITOC 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 104h QSPI_XIP_WRAP _TOC Reserved WTOC 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 108h QSPI_X...

Page 684: ...maintained 14 SSTE Slave Select Toggle Enable While operating in SPI mode with clock phase SCPH set to 0 this bit controls the behavior of the NSS between data frames 0 NSS will stay low and serial c...

Page 685: ...data frame length When the data frame size is programmed to be less than 32 bits the data is automatically right aligned 0x0 0x01 0x02 Reserved 0x03 4bit 0x04 5bit 0x05 6bit 0x1D 30bit 0x1E 31bit 0x1F...

Page 686: ...ion 31 3 Reserved Reserved the reset value must be maintained 2 MHS_EN Microwire Handshaking Enable 0 Handshaking diable 1 Handshaking enable When enabled the QSPI checks for a ready status from the t...

Page 687: ...N 1 24 6 7 QSPI Baud Rate Select Register QSPI_BAUD Address offset 0x14 Reset value 0x0000 0000 Bit field Name Description 31 16 Reserved Reserved the reset value must be maintained 15 0 CLK_DIV 15 0...

Page 688: ...ed 4 0 TXFT_TEI 4 0 Transmit FIFO Threshold to Trigger Empty Interrupt Tx transmission threshold when the number of transmit FIFOs is less than this value an empty interrupt is triggered 24 6 9 QSPI R...

Page 689: ...Reserved the reset value must be maintained 5 0 RXFN 5 0 Number of Receive FIFO 24 6 12 QSPI Status Register QSPI_STS Address offset 0x28 Reset value 0x0000 0006 Bit field Name Description 31 7 Reserv...

Page 690: ...d entries this bit is cleared 1 TXFNF Transmit FIFO Not Full 0 Tx FIFO is full 1 Tx FIFO is not Full Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is ful...

Page 691: ...ield Name Description 31 7 Reserved Reserved the reset value must be maintained 6 XRXOIS XIP Receive FIFO Overflow Interrupt Status 0 Invalid after masking 1 Validafter after masking 5 MMCIS Multi Mas...

Page 692: ...Status 0 Invalid prior to masking 1 Valid prior to masking 5 MMCRIS Multi Master Contention Raw Interrupt Status 0 Invalid prior to masking 1 Valid prior to masking 4 RXFFRIS Receive FIFO Full Raw In...

Page 693: ...maintained 0 TXFOIC Clear Transmit FIFO Overflow Interrupt After reading this register clear the Tx FIFO overflow interrupt status 24 6 17 QSPI Receive FIFO Overflow Interrupt Clear Register QSPI_RXF...

Page 694: ...ister QSPI_MMCI_CLR Address offset 0x44 Reset value 0x0000 0000 Bit field Name Description 31 1 Reserved Reserved the reset value must be maintained 0 MMCIC Clear Multi Master Contention Interrupt Aft...

Page 695: ...field Name Description 31 2 Reserved Reserved the reset value must be maintained 1 TX_DMA_EN Transmit DMA Enable 0 Disable 1 Enable 0 RX_DMA_EN Receive DMA Enable 0 Disable 1 Enable 24 6 22 QSPI DMA...

Page 696: ...0 31 Reset value 0x0000 0000 Bit field Name Description 31 0 DATx 31 0 In the Rx state it is the receive buffer and the read data is automatically right aligned in the Tx state it is the send buffer a...

Page 697: ...QSPI_CTRL0 SPI_FRF 00 This register cannot be written to after the QSPI_EN register is enabled Address offset 0xF4 Reset value 0x0000 0200 Bit field Name Description 31 Reserved Reserved the reset va...

Page 698: ...ion transfer format 00 Instruction and Address will be sent in Standard SPI Mode 01 Instruction will be sent in Standard SPI Mode and Address will be sent in the mode specified by QSPI_CTRL0 SPI_FRF 1...

Page 699: ...ansfer opcode Register QSPI_XIP_INCR_TOC Address offset 0x100 Reset value 0x0000 0000 Bit field Name Description 31 16 Reserved Reserved the reset value must be maintained 15 0 ITOC 15 0 XIP INCR tran...

Page 700: ...h 00 Mode bits length equal to 2 01 Mode bits length equal to 4 10 Mode bits length equal to 8 11 Mode bits length equal to 16 25 24 Reserved Reserved the reset value must be maintained 23 XIP_CT_EN E...

Page 701: ...gth in bits 00 No Instruction 01 4bit 10 8 bit 11 16 bit 8 Reserved Reserved the reset value must be maintained 7 4 ADDR_LEN 3 0 Length of Address to transmit 0x0 No Address 0x1 4bit 0x2 8bit 0x3 12bi...

Page 702: ...nable 0 Not Selected 1 Selected 24 6 33 QSPI XIP Receive FIFO Overflow Interrupt Clear Register QSPI_XIP_RXFOI_CLR Address offset 0x110 Reset value 0x0000 0000 Bit field Name Description 31 1 Reserved...

Page 703: ...t Shenzhen 518057 P R China Bit field Name Description 31 8 Reserved Reserved the reset value must be maintained 7 0 XTOUT 7 0 XIP time out value in terms of AHB XIP time out value in terms of APB Onc...

Page 704: ...MII and RMII two standard interfaces for communication with the physical layer PHY and realizes the transmission and reception of Ethernet data frames Ethernet module complies with the IEEE 802 3 2008...

Page 705: ...automatic discarding of frames when late collision excessive collision excessive deferral and underrun 2 2K byte FIFOs one is TxFIFO for sending the other is RxFIFO for receiving the threshold is conf...

Page 706: ...default configuration is MII mode SMI interface for configuring and managing external PHY devices Ethernet DMA controller accesses the MAC controller through the AHB master interface to control data t...

Page 707: ...ethod Table 25 1 ETH module pin configuration alternate MII Signal RMII Signal Default mapping Remap 1 Remap 2 Remap 3 Pin configuration MDC MDC PC1 Push pull alternate output high speed 50MHz TXD2 PC...

Page 708: ...high speed 50MHz TxD3 PB8 PB7 Push pull alternate output high speed 50MHz 25 4 3 SMI interface SMI is used to access and set the configuration of the PHY It communicates with the external PHY through...

Page 709: ...d mode 2 Set ETH_MACMIIADDR MB to 1 to start receiving data The ETH_MACMIIADDR MB bit can be used to judge whether the transmission is completed When receiving data the ETH_MACMIIADDR MB bit is always...

Page 710: ...ransferred In order to ensure that the received data is normal the active level cannot appear after the SFD on the data line appears MII_Rx_ER Receive error signal keep the valid state for at least on...

Page 711: ...000 to 1111 Normal frame interval 0 1 0000 Normal frame interval 0 1 0001 to 1101 Reserved 0 1 1110 Wrong carrier indication 0 1 1111 Reserved 1 0 0000 to 1111 Normal data receive 1 1 0000 to 1111 Err...

Page 712: ...he clock output pin MCO of the MCU can provide a 50MHz clock signal Figure 25 7 RMII clock source 25 4 6 MAC function description The MAC module performs the encapsulation of transmitted data and rece...

Page 713: ...MAC controller If the frame is not completely written into TxFIFO that is the size of TxFIFO is smaller than the length of the Ethernet frame to be transmitted the data will also be transmitted to MA...

Page 714: ...descriptor with TDES1 FS of 1 is received The clear operation will cause MAC controller to generate a data underflow event and end the transmission of the current frame and return the transmission st...

Page 715: ...f transmission Ethernet controller automatically calculates and inserts checksums when transmitting and detects checksum errors when receiving Only when ETH_DMAOPMOD TSF is configured to 1 that is the...

Page 716: ...um values are not inserted into TCP UDP or ICMP headers The frame data has been transmitted but the data packet taken out by MAC from TxFIFO is smaller than the value indicated by the data length fiel...

Page 717: ...methods of unicast destination address filtering 25 4 6 10 4 HASH or perfect address filter Set ETH_MACFFLT HPF to 1 and set ETH_MACFFLT HUC bit for unicast frames or ETH_MACFFLT HMC bit for multicast...

Page 718: ...is forwarded to application Destination address source address filtering result Table 25 5 Destination address filter result list and Table 25 6 Source address filter result list show the filtering re...

Page 719: ...frame length type field is less than 0x600 MAC will automatically strip the PAD and FCS After the number of bytes transmitted by MAC to RxFIFO reaches the value of the frame length type field all rema...

Page 720: ...d return to the overflow state and the overflow counter will be incremented accordingly If RxFIFO works in store and forward mode MAC filter and discard all error frames but by setting ETH_DMAOPMOD FE...

Page 721: ...If there is no frame underflow no carrier carrier loss excessive deferral late collision excessive collision or Jabber timeout error in the transmitted frame it is considered that the transmission pro...

Page 722: ...3 command Reserved Filter 2 command Reserved Filter 1 command Reserved Filter 0 command Wakeup frame filter register 5 Filter 3 offset Filter 2 offset Filter 1 offset Filter 0 offset Wakeup frame filt...

Page 723: ...nd recognized by the Ethernet module and triggers a wake up event The frame format of the Magic Packet wake up frame is as follows 6 bytes of all 1 0xFFFF FFFF FFFF at any position after the destinati...

Page 724: ...to normal state 25 4 8 Ethernet DMA function description The dedicated DMA controller of Ethernet module can realize the frame data transmission between FIFO and system storage reducing the intervent...

Page 725: ...lignment types supported by Ethernet DMA controller include byte alignment halfword alignment and word alignment So the application can configure the transmit data buffer address and receive data buff...

Page 726: ...igured to be large enough to store a complete frame RDES0 FS and RDES0 LS will be set in the same descriptor The actual received frame length can be obtained through these bits of RDES0 FL 13 0 Applic...

Page 727: ...unt TDES2 Buffer 1 address Timestamp low TDES3 Buffer 2 address Next descriptor address Timestamp high TDES0 Transmit descriptor word 0 Bit field Name Description 31 OWN Occupancy bit 0 Indicates that...

Page 728: ...1 Data underflow error 14 JT Jabber timeout This bit is only set when ETH_MACCFG JD bit is reset 0 No Jabber timeout occurred 1 A Jabber timeout occurred at MAC sender 13 FF Frame clear When set to 1...

Page 729: ...0 Collision count This 4 bit value records the number of collision that occurred before frame was transmitted These bits have no effect when TDES0 EC is 1 2 ED Excessive deferral This bit is valid wh...

Page 730: ...fields but do not calculate checksums of pseudo headers 11 Enable calculation and insertion of checksum of hardware IP header and data field and also calculate checksum of pseudo header 26 DC Disable...

Page 731: ...tor type is chain or ring After data is transmitted DMA can use them to store the upper 32 bits of the frame s timestamp When the value of TDES3 represents the physical address of buffer 2 TDES1 TCH 0...

Page 732: ...ter completing a complete frame transmission ETH_DMASTS TI transmit status bit will be set only when TDES1 IC is 1 If DMA interrupt is enabled corresponding interrupt will be entered Then DMA controll...

Page 733: ...ing in cut through threshold mode and the received frame length is greater than or equal to the preset receive threshold or working in store and forward mode and a complete frame is stored in the RxFI...

Page 734: ...tamp low RDES3 Buffer 2 address Next descriptor address Timestamp high RDES0 Receive descriptor word 0 Bit field Name Description 31 OWN Occupancy bit 0 Indicates that CPU occupies descriptor 1 Indica...

Page 735: ...as occurred 11 OE Overflow error This bit is set when RxFIFO has overflowed and part of the received frame has been transferred to input buffer 0 No overflow error occurred 1 RxFIFO overflow occurred...

Page 736: ...1 A watchdog timeout occurred while receiving a frame and current received frame will be truncated 3 RE Receive error This bit indicates that the valid interface signal Rx_ER is received when the Rx_...

Page 737: ...descriptor Note When RER 1 even if this bit is set the next descriptor will return the list base address 23 22 Reserved Reserved the reset value must be maintained 21 11 RBS2 10 0 Receive buffer 2 si...

Page 738: ...rement ETH_DMAMFBOCNT MISFRMCNT missed frame count by 1 repeat the process if there is more than one frame in RxFIFO If ETH_DMAOPMOD DFF 1 the frame at the top of RxFIFO will not be dropped When RDES0...

Page 739: ...available to 1 9 When any write operation is performed to ETH_DMARXPD register or RxFIFO receives the next frame of data the suspend state can be exited When DMA exits suspended state DMA operation ju...

Page 740: ...resolution of the timestamp counter and the time synchronization accuracy between the master node and the slave node is about 0 1us Synchronization accuracy The accuracy of time synchronization depend...

Page 741: ...0 of the timestamp low register represent the sub second value of the system time the precision is equal to 109 ns 231 0 46ns In order to achieve a system time accuracy of 20ns the value of the sub se...

Page 742: ...add the offset values of timestamp high and low update registers to the original system time 3 Wait for ETH_PTPTSCTRL TSUPDT bit to be cleared Steps to update system time with fine adjustment 1 Calcul...

Page 743: ...Mbps 100Mbps communication speed etc and configure the information of the external PHY register to the ETH_MACCFG register 5 Initialize Ethernet DMA module Configure ETH_DMABUSMOD ETH_DMARXDLADDR ETH_...

Page 744: ...cated in Rx_CLK domain there may be a delay caused by the difference between the HCLK and Rx_CLK clock frequencies from the time the application reads PMT register until these flags are cleared To avo...

Page 745: ...4h ETH_MACMIIDAT Reserved MD 15 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 018h ETH_MACFLWCTRL PT 15 0 Reserved DZQP Reserved PLT 1 0 UP RFE TFE FCB_BPA Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 746: ...ed Reset Value 0 0 0 108h ETH_MMCTXINT Reserved TXGFRMIS Reserved TXMCOLGFIS TXSCOLGFIS Reserved Reset Value 0 0 0 10Ch ETH_MMCRXINTMSK Reserved RXUCGFIM Reserved RXALIGNERFIM RXCRCERFIM Reserved Rese...

Page 747: ...Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1008h ETH_DMARXPD RPD 31 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 100Ch ETH_DMARXDLADDR...

Page 748: ...2048 bytes will be truncated 1 Turn off receive watchdog timer and MAC can receive frames with a maximum length of 16383 bytes 22 JD Disable Jabber detection 0 Allows transmit frames of up to 2048 by...

Page 749: ...these bits in ETH_MACCFG BL 1 0 after a collision 1 MAC will only attempt to send 1 time If a collision occurs on MII MAC will abort the transmission and report an excessive collision error in the tra...

Page 750: ...AC enables receive state machine 1 0 Reserved Reserved the reset value must be maintained 25 5 3 ETH MAC frame filter register ETH_MACFFLT Address offset 0x0004 Reset value 0x0000 0000 MAC Frame Filte...

Page 751: ...e frames and whether to process pause control frames depends only on the value of ETH_MACFLWCTRL RFE 00 MAC does not forward any control frames to the application 01 MAC forwards control frames other...

Page 752: ...descriptor is always 0 0 Disable promiscuous mode 1 Enable promiscuous mode 25 5 4 ETH MAC HASH list high register ETH_MACHASHHI Address offset 0x0008 Reset value 0x0000 0000 A 64 bit HASH list can be...

Page 753: ...PHY register to be accessed 5 Reserved Reserved the reset value must be maintained 4 2 CR 2 0 Clock range These bits are used to configure the clock of MDC according to the frequency of HCLK value MD...

Page 754: ...ol register ETH_MACFLWCTRL Address offset 0x0018 Reset value 0x0000 0000 This register is used for the generation and reception of configuration control PAUSE frames Bit field Name Description 31 16 P...

Page 755: ...w control enable bit When this bit is set to 1 MAC will turn off the transmitter for the specified time the value of the Pause Time field in the received frame 0 MAC does not parse PAUSE frames 1 MAC...

Page 756: ...eset value must be maintained 16 ETC 12 bit VLAN tag comparison bits This bit selects VLAN tag to be compared with ETH_MACVLANTAG VLTI 11 0 12 bits or ETH_MACVLANTAG VLTI 15 0 16 bits 0 Use all 16 bit...

Page 757: ...000 0000 Bit field Name Description 31 RWKUPFLTRST Remote wakeup frame filter register pointer reset 0 No effect 1 Reset ETH_MACRMTWUFRMFLT register pointer which is automatically cleared to 0 after t...

Page 758: ...r mode is exited the hardware will automatically clear this bit to 0 This bit can only be set when ETH_MACPMTCTRLSTS RWKPKTEN or ETH_MACPMTCTRLSTS MGKPKTEN is 1 25 5 12 ETH MAC interrupt status regist...

Page 759: ...5 13 ETH MAC interrupt mask register ETH_MACINTMSK Address offset 0x003C Reset value 0x0000 0000 Bit field Name Description 31 10 Reserved Reserved the reset value must be maintained 9 TSIM Timestamp...

Page 760: ...set 0x0044 Reset value 0xFFFF FFFF Bit field Name Description 31 0 ADDRLO 31 0 MAC address 0 low 32 bits These bits contain the lower 32 bits of the 6 byte MAC address 0 These bits are used as the add...

Page 761: ...l bit are as follows MBC 5 ETH_MACADDR1HI 15 8 MBC 4 ETH_MACADDR1HI 7 0 MBC 3 ETH_MACADDR1LO 31 24 MBC 2 ETH_MACADDR1LO 23 16 MBC 1 ETH_MACADDR1LO 15 8 MBC 0 ETH_MACADDR1LO 7 0 23 16 Reserved Reserved...

Page 762: ...rresponding byte of the destination source address of the received frame with the corresponding byte of the MAC address 2 The MAC address bytes corresponding to each control bit are as follows MBC 5 E...

Page 763: ...k byte control bits When a bit is set to 1 MAC will ignore the comparison of the corresponding byte of the destination source address of the received frame with the corresponding byte of the MAC addre...

Page 764: ...e MMC counter the counter is not reset 1 After reading the MMC counter the counter is reset 1 CNTSTOPRO Counter stop rollover 0 After the counter reaches the maximum value it will start counting from...

Page 765: ...um value 5 RXCRCERFIS Received frame CRC error status 0 CRC error received frame counter value has not reached half of the maximum value 1 CRC error received frame counter value reaches half of the ma...

Page 766: ...half of the maximum value 13 0 Reserved Reserved the reset value must be maintained 25 5 25 ETH MMC receive interrupt mask register ETH_MMCRXINTMSK Address offset 0x010C Reset value 0x0000 0000 Bit fi...

Page 767: ...ed the reset value must be maintained 15 TXMCOLGFIM Transmit good frame interrupt mask bit after more than 1 collision 0 Do not mask the interrupt that occurs when ETH_MMCTXINT TXMCOLGFIS is 1 1 Mask...

Page 768: ...ffset 0x0150 Reset value 0x0000 0000 This register is used to count the number of frames successfully transmitted after more than one collision in half duplex mode Bit field Name Description 31 0 CNT...

Page 769: ...n 31 0 CNT 31 0 CRC error received frame counter These bits are a counter of frames with CRC errors in the received frame 25 5 31 ETH MMC alignment error received frame counter register ETH_MMCRXFAECN...

Page 770: ...EG Timestamp adder register update bit This bit is cleared to 0 after the update is complete This bit must be read as 0 before being set to 1 0 Do not update the value of the timestamp addend register...

Page 771: ...p function 1 Enable timestamp function of received and transmitted frames Note The system time needs to be re initialized every time this bit is set to 1 25 5 34 ETH PTP subsecond increment register E...

Page 772: ...d value of the system time Bit field Name Description 31 PN System time positive or negative sign 0 Time value is positive value 1 Time value is negative value 30 0 TSSS 30 0 System time subsecond The...

Page 773: ...IT is set to 1 this bit should be 0 When ETH_PTPTSCTRL TSUPDT is set to 1 and this bit is 0 the timestamp update value is added to the system time otherwise the timestamp update value is subtracted fr...

Page 774: ...71C Reset value 0x0000 0000 Bit field Name Description 31 0 TTS 31 0 Target timestamp high These bits represent the seconds value of the target time If the timestamp value equals or exceeds the target...

Page 775: ...sequent transfers and addresses are aligned 24 PBLX8 8x PBL mode 0 The PBL value is used as the DMA transfer length value 1 The PBL value is multiplied by 8 as the DMA transfer length value For specif...

Page 776: ...r If ETH_DMABUSMOD USP 1 these bits are only used for TxDMA transfers If ETH_DMABUSMOD USP 0 these bits are used for both TxDMA and RxDMA transfers 000001 The maximum number of data transfers is 1 000...

Page 777: ...riptor is occupied by the CPU TDES0 OWN 0 Any value can be written to this register to enable sending queries Bit field Name Description 31 0 TPD 31 0 Transmit query request bit Write any value to the...

Page 778: ...er points to the beginning of the receive descriptor queue Descriptor queues are located in physical memory and their addresses must be word aligned Writing to this register is only allowed when recep...

Page 779: ...r them while writing 0 is invalid By setting the corresponding bits in the ETH_DMAINTEN register the interrupts triggered by these bits except reserved bits of bit0 bit16 can be masked Bit field Name...

Page 780: ...DMA transfer of data EB 1 0 Error during write transfer 1 Error during read transfer EB 2 0 Error during data buffer access 1 Error during descriptor access 22 20 TPS 2 0 Transmit process status These...

Page 781: ...hdog timeout ETH_DMASTS 10 Early send interrupt ETH_DMASTS 13 Bus fatal error Only unmasked interrupts will affect this bit The value of this bit is bound to the above bits After it is set to 1 this b...

Page 782: ...Receive overflow status When this bit is 1 if some frame data has been forwarded to the memory set RDES0 OE to 1 0 No receive data overflow error occurred 1 Data overflow error occurred during frame...

Page 783: ...ward it to the application and the value of ETH_DMAOPMOD RTC will be ignored 24 DFF Do not clear received frames 0 When the receive descriptor is not available or the receive buffer is not available t...

Page 784: ...npredictable consequences may occur if this bit is set before other DMA registers have been set 12 8 Reserved Reserved the reset value must be maintained 7 FEF Forward error frames 0 When RxFIFO is op...

Page 785: ...information of the previous frame 1 SR Start stop receive 0 RxDMA enters stop mode after forwarding the current received frame Holds the position of the next receive descriptor in the receive descrip...

Page 786: ...TS 9 Receive watchdog timeout ETH_DMASTS 10 Early transmit interrupt ETH_DMASTS 13 Bus fatal error 14 ERIE Early receive interrupt enable 0 Mask early receive interrupt 1 When ETH_DMAINTEN NISE is 1 e...

Page 787: ...enable 0 Mask transmit buffer unavailable interrupt 1 When ETH_DMAINTEN NISE is 1 enable transmit buffer unavailable interrupt 1 TPSE Transmit process stop interrupt enable 0 Mask transmit process to...

Page 788: ...5 51 ETH DMA current transmit descriptor address register ETH_DMACHTXDESC Address offset 0x1048 Reset value 0x0000 0000 This register points to the start address base address of the transmit descript...

Page 789: ...Reset value 0x0000 0000 This register points to the address of the transmit buffer that TxDMA is reading Bit field Name Description 31 0 ADDR 31 0 Transmit buffer address pointer These bits are clear...

Page 790: ...evel COMP system connection block diagram The COMP module supports a maximum of seven independent comparators which are connected to the APB1 bus Figure 26 1 Comparator1 and comparator2 connection dia...

Page 791: ...DAC1 PA4 VREF1 VREF2 DAC2 PA5 PB12 COMP Interrupt PB10 PC10 PA2 TIM1_BKIN TIM1_OCrefClear TIM1_IC1 TIM2_IC3 TIM2_OCrefClear TIM4_IC2 TIM4_OCrefClear TIM8_BKIN TIM5_IC2 TIM1_BKIN TIM8_BKIN PB15 PC4 DA...

Page 792: ...PC9 COMP5 COMP6 PD10 Polarity Selection Polarity Selection TIM1_BKIN TIM8_OCrefClear TIM2_IC4 TIM3_IC4 TIM3_OCrefClear TIM4_IC4 TIM4_OCrefClear TIM8_BKIN TIM2_OCrefClear TIM8_IC1 TIM1_BKIN TIM8_BKIN T...

Page 793: ...orm window comparators You can wake the system from Sleep mode or STOP0 mode by generating an interrupt Filter window size can be configured Filter threshold size can be configured The sampling freque...

Page 794: ...rator function The output of a comparator can be output to an I O port Each comparator has a different remapped port You can configure the comparator register COMPx_CTRL OUTTRG 3 0 to enable the corre...

Page 795: ...M1_BKIN TIM1_BKIN TIM1_BKIN TIM1_BKIN TIM1_BKIN TIM1_BKIN TIM1_BKIN 0010 TIM1_IC1 TIM1_IC1 TIM1_IC1 TIM3_IC3 TIM2_IC4 TIM2_IC1 TIM2_IC1 0011 TIM1_OCre fclear TIM1_OCrefcl ear TIM1_OCrefcl ear TIM3_OCr...

Page 796: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 010h COMP1_CTRL Reserved INPDAC OUT BLKING 2 0 HYST 1 0 POL OUTSEL 3 0 INPSEL 2 0 INMSEL 2 0 EN Reset Value 0 0 0 0...

Page 797: ...0 0 0 0 0 0 04Ch Reserved 050h COMP5_CTRL Reserved INPDAC OUT BLKING 2 0 HYST 1 0 POL OUTSEL 3 0 INPSEL 2 0 INMSEL 2 0 EN Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 054h COMP5_FILC Reserved SA...

Page 798: ...eset Value 0 0 0 0 0 0 0 090h COMP_INTSTS Reserved CMP7IS CMP6IS CMP5IS CMP4IS CMP3IS CMP2IS CMP1IS Reset Value 0 0 0 0 0 0 0 094h COMP_VREFSCL Reserved VV2TRM 5 0 VV2EN VV1TRM 15 0 VV1EN Reset Value...

Page 799: ...n selection Note For the specific enumeration value correspondence please refer to chapter 26 5 Comparator interconnection 6 4 INPSEL 2 0 Comparator non inverting input selection Note For the specific...

Page 800: ...1 and 2 are not in window mode 1 Comparators 1 and 2 are in window mode 26 7 4 COMP lock register COMP_LOCK Address offset 0x84 Reset value 0x0000 0000 Bit field Name Description 31 7 Reserved Reserve...

Page 801: ...CMP7IEN 2 CMP3IEN Same function as CMP7IEN 1 CMP2IEN Same function as CMP7IEN 0 CMP1IEN Same function as CMP7IEN 26 7 6 COMP interrupt status register COMP_INTSTS Address offset 0x90 Reset value 0x00...

Page 802: ...te This value is required to be greater than SAMPW 2 0 FILEN Filter enable 0 Disable 1 Enable 26 7 8 COMP filter frequency division register COMPx_FILP Address offset 0x18 0x28 0x38 0x48 0x58 0x68 0x7...

Page 803: ...m Address Nations Tower 109 Baoshen Road Hi tech Park North Nanshan District Shenzhen 518057 P R China Bit field Name Description 7 VREF2EN VREF2 voltage scaler 0 disable 1 enable 6 1 VREF1SET 5 0 VRE...

Page 804: ...odes can be configured Independent op amp mode Voltage follower Programmable gain amplifier Differential op amp of two op amps Programmable gain settings are 2X 4X 8X 16X 32X times Gain bandwidth 4MHz...

Page 805: ...nstech com Address Nations Tower 109 Baoshen Road Hi tech Park North Nanshan District Shenzhen 518057 P R China Figure 27 1 Block diagram of OPAMP1 and OPAMP2 connection diagram OPAMP1 OPAMP2 PA1 PA3...

Page 806: ...P R China Figure 27 2 Block diagram of OPAMP3 and OPAMP4 connection diagram 27 1 2 Internal connection between OPAMP and COMP OPAMP1 OPAMP2 COMP1 COMP2 COMP3 ADC1 and ADC2 constitute a group of analo...

Page 807: ...VREF2 DAC2 PA5 PB14 PE7 DAC1 PA4 VREF1 VREF2 DAC2 PA5 PB12 TIM1_BKIN TIM1_OCrefClear TIM1_IC1 TIM2_IC2 TIM2_OCrefClear TIM3_IC2 TIM3_OCrefClear TIM8_BKIN TIM1_BKIN TIM1_OCrefClear TIM1_IC1 TIM2_IC1 TI...

Page 808: ...7 TIM1_BKIN TIM8_OCrefClear TIM3_IC3 TIM4_IC3 TIM4_OCrefClear TIM5_IC3 TIM8_BKIN COMP Interrupt PC5 PB12 PC11 COMP Interrupt PA11 PB0 PB6 PB11 COMP Interrupt PA12 PB7 PC9 DAC2 PA5 COMP4 COMP5 COMP6 OP...

Page 809: ...tion system Four completely independent OPAMPs At this time the gain is determined by the external resistor network It can also be cascaded as required to form the required amplification gain As shown...

Page 810: ...put voltage through a built in resistor feedback network OPAMPx_CS MOD 2b 10 is a PGA function that supports 2 4 8 16 32 magnification OPAMPx_CS VMSSEL or OPAMPx_CS VMSEL pins must be set to float OPA...

Page 811: ...R China Figure 27 7 Internal gain mode 27 2 4 OPAMP with filter internal gain mode In this mode the amplification voltage is adjustable supports 2 4 8 16 32 and the OPAMPx_CS VPSSEL or OPAMAPx_CS VPS...

Page 812: ...gured by VPSSEL VMSSEL as input otherwise use VPSEL VMSEL When TIM8_CC6 is high OPAMP3 and OPAMP4 select the port configured by VPSSEL VMSSEL as input otherwise use VPSEL VMSEL Set OPAMPx_CS TCMEN to...

Page 813: ...d Name Description 31 22 Reserved Retained the reset value must be maintained 21 19 VPSSEL 2 0 OPAMP non inverted input secondary selection VPSSEL 2 0 OPAMP1 OPAMP2 OPAMP3 OPAMP4 000 PA1 PA7 PC9 PC3 0...

Page 814: ...mode enabled 0 Normal mode 1 Calibration mode 10 8 VPSEL 2 0 OPAMP non inverted input selection VPSEL 2 0 OPAMP1 OPAMP2 OPAMP3 OPAMP4 000 PA1 PA7 PC9 PC3 001 PA3 PB0 PA1 DAC1 PA4 010 DAC2 PA5 PE8 DAC2...

Page 815: ...lifier Enable 0 Disable 1 Enable 27 3 3 OPAMP Lock register OPAMP_LOCK Offset address 0x40 Reset value 0x0000 0000 Bit field Name Description 31 4 Reserved Reserved the reset value must be maintained...

Page 816: ...CMOS sensor The polarity of input pixel clock DVP_PCLK frame synchronization signal DVP_VSYNC and horizontal synchronization signal DVP_HSYNC can be independently configured Support 8x 32bit FIFO FIFO...

Page 817: ...high and capture data on the falling edge of DVP_PCLK to receive data correctly DVP data is only valid when the capture enable bit register DVP_CTRL CAPTURE is 1 and the capture enable bit must be 1 a...

Page 818: ...needed The DVP module only stores the area data that needs to be reserved into the FIFO and other data are automatically discarded DVP_WST VST configures the starting line of the capture area In the v...

Page 819: ...will be reported only after the corresponding interrupt enable bit in DVP_INTEN is turned on DVP_MINTSTS is the register of interrupt status that reported to system and users generally only use this...

Page 820: ...Reset Value 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 004h DVP_STS Reserved FCNT 2 0 FNE Reset Value 0 0 0 0 008h DVP_INTSTS Reserved HERRIS VERRIS FOIS FWIS FFIS FEIS LEIS LSIS FMEIS FMSIS Reset Value 0 0 0 0...

Page 821: ...lines 001 Capture 1 line of each 2 lines 010 Capture 1 line of each 3 lines 011 Capture 1 line of each 4 lines 100 Capture 1 line of each 5 lines 101 Capture 1 line of each 6 lines 110 Capture 1 line...

Page 822: ...s automatically cleared 1 Continuous mode After transmitting a frame of data the CAPTURE bit is not cleared and continues to wait for the next frame synchronization signal 0 CAPTURE Capture enable In...

Page 823: ...number of received data lines is less than the configured number of data lines per frame a VSYNC error is generated VSYNC arrives early 0 No error 1 There is a VSYNC error 7 FOIS FIFO overflow status...

Page 824: ...MSIS Frame start state Software write 0 to clear 0 Frame not started 1 Frame has started 28 4 5 DVP Interrupt Enable Register Address offset 0x0c Reset value 0x0000 0000 Bit field Name Description 31...

Page 825: ...interrupt enable 0 Disable line start interrupt 1 Enable line start interrupt 1 FMEIE End of frame interrupt enable 0 End of frame interrupt is not enabled 1 Enable end of frame interrupt 0 FMSIE Sta...

Page 826: ...a length in the FIFO has reached DVP_CTRL FWM 2 0 and interrupt triggered 5 FFMIS FIFO full interrupt status This bit is related to the real time status of the FIFO and can only be cleared by reading...

Page 827: ...number the first line starts at 0 12 11 Reserved Reserved the reset value must be maintained 10 0 HST 10 0 Starting pixel number the first pixel starts at 0 28 4 8 DVP image size register DVP_WSIZE Ad...

Page 828: ...il info nationstech com Address Nations Tower 109 Baoshen Road Hi tech Park North Nanshan District Shenzhen 518057 P R China Bit field Name Description 31 24 DAT3 7 0 Data byte 3 23 16 DAT2 7 0 Data b...

Page 829: ...can be restored and the corresponding program can continue to be executed The hardware debugging module of the N32G45x kernel can be used when it is connected to the debugger when it is not disabled...

Page 830: ...debug interface by default If you need to switch the debug interface you can switch between SWD interface and JTAG interface through the following operations JTAG debug to SWD debug switch 1 Sending...

Page 831: ...2G45x can provide a variety of low power consumption modes refer to Power control PWR for details When debugging ensure that the FCLK and HCLK of the kernel are on and provide the necessary clock for...

Page 832: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000h DBG_ID SRAM 3 0 Reserved DEV_NUM_L 3 0 FLASH 3 0 DEV_NUM_H 3 0 DEV_NUM_M 3 0 REV_NUM_H 3 0 REV_NUM_L 3 0 Res...

Page 833: ...lue 0x0000 0000 not reset by system reset Bit field Name Description 31 22 Reserved Reserved the reset value must be maintained 21 CAN2_STOP When the kernel enters the debugging state CAN2 stops runni...

Page 834: ...STANDBY mode is the same as resetting except that some status bits indicate that the microcontroller has just exited from the STANDBY state 1 FCLK ON HCLK ON The digital circuit part is not powered d...

Page 835: ...ress Nations Tower 109 Baoshen Road Hi tech Park North Nanshan District Shenzhen 518057 P R China Bit field Name Description clock system when exiting from sleep mode 1 FCLK ON HCLK ON In sleep mode b...

Page 836: ...med during manufacture and any MCU microcontroller is guaranteed to be unique under any circumstances It can be read by user applications or external devices through CPU or SWD interface and cannot be...

Page 837: ...ogies Inc Tel 86 755 86309900 Email info nationstech com Address Nations Tower 109 Baoshen Road Hi tech Park North Nanshan District Shenzhen 518057 P R China Version history Date Version Remark 2022 7...

Page 838: ...gram and test the functionality and safety of any application made of this information and any resulting product In no event shall NATIONS be liable for any direct indirect incidental special exemplar...

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