438
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
T
𝑊𝑊𝐷𝐺
= 𝑇
𝑃𝐶𝐿𝐾1
× 4096 × 2
𝑇𝐼𝑀𝐸𝑅𝐵
× (𝑇[5: 0] + 1)
In which:
T
WWDG
: WWDG timeout
T
PCLK1
:APB1 clock interval in ms
Minimum-maximum timeout value at PCLK1 = 36MHz
Table 17-1 Maximum and minimum counting time of WWDG
TIMERB
Maximum counting (ms)
Minimum counting (ms)
0
7.28
0.113
1
14.56
0.227
2
29.12
0.455
3
58.25
0.910
Debug mode
In debug mode (Cortex-M4 core stops), WWDG counter will either continue to work normally or stops, depending
on DBG_CTRL.WWDG_STOP bit in debug module. If this bit is set to ‘1’, the counter stops. The counter works
normally when the bit is ‘0’. See the chapter on debugging module for details 29.3.2.
User interface
17.6.1
WWDG configuration flow
1)
Configure RCC_APB1PCLKEN.WWDGEN[11] bit to enable the clock of WWDG module;
2)
Software setting WWDG_CFG.TIMERB[8:7] bits to configure pre-scale factor for WWDG.
3)
Software configure WWDG_CTRL.T[6:0] bits, setting starting value of counter. Need to set
WWDG_CTRL.T[6] bit to 1, preventing reset right after enable.
4)
Configure WWDG_CFG.W[6:0] bits to configure upper boundary window value;
5)
Setting WWDG_CTRL.ACTB[7] bit to enable WWDG;
6)
Software operates WWDG_STS.EWINTF[0] bit to clear wake-up interrupt flag;
7)
Configure WWDG_CFG.EWINT[9] bit to enable early wake-up interrupt.
