Nations N32G45 Series, User Manual

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311 / 838
Nations Technologies Inc.
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Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit field Name Description
current timer (via TRGO) and its slaves. This is useful when several timers are required to be
synchronized to a single external event.
6:4 TSEL[2:0] Trigger selection
These 3 bits are used to select the trigger input of the synchronous counter.
000: Internal trigger 0 (ITR0) 100: TI1 edge detector (TI1F_ED)
001: Internal trigger 1 (ITR1) 101: Filtered timer input 1(TI1FP1)
010: Internal trigger 2 (ITR2) 110: Filtered timer input 2 (TI2FP2)
011: Internal trigger 3 (ITR3) 111: External triggered Input (ETRF)
For more details on ITRx, see Table 11-3 below.
Note: These bits must be changed only when not in use (e. g. TIMx_SMCTRL.SMSEL=000) to avoid
false edge detection at the transition.
3 Reserved Reserved, the reset value must be maintained
2:0 SMSEL[2:0] Slave mode selection
When an external signal is selected, the active edge of the trigger signal (TRGI) is linked to the
selected external input polarity (see input control register and control register description)
000: Disable slave mode. If TIMx_CTRL1.CNTEN = 1, the prescaler is driven directly by the
internal clock.
001: Encoder mode 1. According to the level of TI2FP2, the counter up-counting or down-counting
on the edge of TI1FP1.
010: Encoder mode 2. According to the level of TI1FP1, the counter up-counting or down-counting
on the edge of TI2FP2.
011: Encoder mode 3. According to the input level of another signal, the counter up-counting or
down-counting on the edges of TI2FP1 and TI2FP2.
100: Reset mode. On the rising edge of the selected trigger input (TRGI), the counter is reinitialized
and the shadow register is updated.
101: Gated mode. When the trigger input (TRGI) is high, the clock of the counter is enabled. Once
the trigger input becomes low, the counter stops counting, but is not reset. In this mode, the start and
stop of the counter are controlled.
110: Trigger mode. When a rising edge occurs on the trigger input (TRGI), the counter is started but
not reset. In this mode, only the start of the counter is controlled.
111: External clock mode 1. The counter is clocked by the rising edge of the selected trigger input
(TRGI).
Note: Do not use gated mode if TI1F_ED is selected as the trigger input
(TIMx_SMCTRL.TSEL=100). This is because TI1F_ED outputs a pulse for each TI1F transition,
whereas gated mode checks the level of the triggered input.
Table 11-3 TIMx internal trigger connection
Slave timer ITR0 (TSEL = 000) ITR1 (TSEL = 001) ITR2 (TSEL = 010) ITR3 (TSEL = 011)
TIM1 TIM5 TIM2 TIM3 TIM4
TIM8 TIM1 TIM2 TIM4 TIM5