Nations N32G45 Series, User Manual

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206 / 838
Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Table 9-1 ADC pins
Name Types Description
V
DDA
Input, analog power supply Equivalent to V
DD
analog power supply and: 1.8V ≤ V
DDA
≤
V
DD
(3.6V)
V
SSA
Input, analog power supply ground Equivalent to V
SS
analog power supply ground
V
REF+
Input, analog reference positive Positive reference voltage used by ADC, 1.8V ≤ V
REF+
≤ V
DDA
V
REF-
Input, analog reference negative The low/negative reference voltage used by the ADC, V
REF- =
V
SSA
ADCx_IN Analog input signal Analog external input channels
Note:
1
．
V
DDA
and V
SSA.
They should be separately connected to V
DD
and V
SS
.
2
．
If there is a V
REF
- Pins (depending on the package), it must be connected to VSSA.
3
．
If there are no VREF+ pins (depending on the package), try to ensure that the voltage values of VDDA and VDD are the same, otherwise
the ADC accuracy will be affected.
4
．
External channel reference data sheet.
9.3.1 ADC clock
An ADC requires three clocks, HCLK, ADC_CLK and ADC_1MCLK.

HCLK is used for the register access.

ADC_CLK is the working clock of ADC. ADC_CLK has two sources (HCLK divider or PLL divider). HCLK
divider and system are synchronous clock, while PLL divider and system are asynchronous clock. The advantage
of using a synchronous clock is that there is no uncertainty when triggering the ADC to respond to the trigger.The
advantage of using PLL's divider clock is that the ADC's working clock can be handled independently without
affecting other modules attached to the HCLK

ADC_1MCLK for internal timing function, configured in RCC, frequency size must be configured to 1MHz
Note:
1. Configuration PLL as a clock source, up to 72 MHz, support frequency division 1,2,4,6,8,10,12,16,32,
64,128,256
2. The AHB_CLK frequency division can be configured as a working clock up to 72MHz. The AHB_CLK frequency
division can be 1,2,4,6,8,10,12,16,32
3. When switching the ADC_1M clock source, you need to ensure that the HSI clock is turned on