National Semiconductor LMX2531LQ1415E Operating Instructions Manual Download | Manualshive

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L M X 2 5 3 1 L Q 1 3 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S

Mid Layer 1 "Ground Plane" (15 Mils Down FR4)

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Summary of Contents for LMX2531LQ1415E

Page 1: ...X2531LQ1415E Evaluation Board Operating Instructions National Semiconductor Corporation Timing Devices Business Group 10333 North Meridian Suite 400 Indianapolis IN 46290 LMX2531LQ1415EFPEB Rev 4 02 2008 ...

Page 2: ...DIVIDE BY 2 DISABLED 6 FREE RUNNING VCO PHASE NOISE INTERNAL DIVIDE BY 2 ENABLED 7 FRACTIONAL SPURS INTERNAL DIVIDE BY 2 DISABLED 8 FRACTIONAL SPURS INTERNAL DIVIDE BY 2 ENABLED 9 INTEGER SPURS INTERNAL DIVIDE BY 2 DISABLED 10 INTEGER SPURS INTERNAL DIVIDE BY 2 ENABLED 11 CODELOADER SETTINGS 12 SCHEMATIC 17 BILL OF MATERIALS 18 TOP LAYER 19 MID LAYER 1 GROUND PLANE 20 MID LAYER 2 POWER 21 BOTTOM L...

Page 3: ...erators tend to be very noisy and should be used with caution If a signal generator is used the signal generator phase noise contribution can be reduced by setting the signal to 80 MHz and dividing this down to a phase detector frequency of 10 MHz Set up the CodeLoader software o Select the proper part from the menu as Select Part PLL VCO LMX2531LQ1415E o Select the proper mode from the Mode menu ...

Page 4: ...r is used ensure that the RF is set to ON If using the lower frequency band DIV2 1 understand the VCO frequency in CodeLoader should be twice the frequency at the Fout pin Ensure the VCO FREQUENCY CAL bits on the Bits Pins tab are correct Ensure the loop filter is optimized if the charge pump current phase detector frequency or loop filter values have been changed from their original settings Ensu...

Page 5: ... 3 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Phase Noise Output Frequency 1415 MHz Internal Divide by 2 Disabled DIV2 0 Output Frequency 707 5 MHz Internal Divide by 2 Enabled DIV2 1 5 ...

Page 6: ...of the VCO In order to take these plots the E5052 phase nose analyzer was used The method was to lock the PLL to the proper frequency then disable the EN_PLL EN_PLLLDO1 and EN_PLLLDO2 bits The equipment needs to be able to track the VCO phase noise to measure in this way and one can not let the VCO drift too far off in frequency If this kind of equipment is not available the VCO phase noise can al...

Page 7: ...d was to lock the PLL to the proper frequency then disable the EN_PLL EN_PLLLDO1 and EN_PLLLDO2 bits The equipment needs to be able to track the VCO phase noise to measure in this way and one can not let the VCO drift too far off in frequency If this kind of equipment is not available the VCO phase noise can also be measured by making a very narrow loop bandwidth filter When divide by 2 is enabled...

Page 8: ...ncy of 1360 25 MHz is 77 6 dBc Worst case channels occur at exactly one channel spacing above or below a multiple of the crystal frequency There is another sub fractional spur that can be impacted by modulator order and dithering Fractional Spur at 250 kHz offset at a worst case frequency of 1420 25 MHz is 77 4 dBc Fractional Spur at 250 kHz offset at a worst case frequency of 1260 25 MHz is 73 8 ...

Page 9: ... MHz is 80 4 dBc Since this mode uses the divide by 2 mode the channel spacing here is actually 125 kHz The spur at 125 kHz could be eliminated by doubling the channel spacing before the divider Spur at 250 kHz offset for a frequency of 615 125 MHz is 85 7 dBc Spur at 250 kHz offset for a frequency of 630 125 MHz is 84 5 dBc The sub fractional spur at 125 kHz offset of 79 dBc is also visible 9 ...

Page 10: ... A T I N G I N S T R U C T I O N S Integer Spurs Internal Divide by 2 Disabled Spur at 10 MHz offset for a frequency of 1360 MHz is 90 1 dBc Spur at 10 MHz offset for a frequency of 1415 MHz is 88 8 dBc Spur at 10 MHz offset for a frequency of 1470 MHz is 85 5 dBc 10 ...

Page 11: ...rs Internal Divide by 2 Enabled Spur at 10 MHz offset for a frequency of 680 MHz is below the spectrum analyzer noise floor Spur at 10 MHz offset for a frequency of 707 5 MHz is below the spectrum analyzer noise floor Spur at 10 MHz offset for a frequency of 735 MHz is below the spectrum analyzer noise floor 11 ...

Page 12: ... 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S CodeLoader Settings CodeLoader is designed to run many devices When CodeLoader is first started it is necessary to select the correct device 12 ...

Page 13: ...menu This restores bit settings and frequencies but not the Port Setup information The default reference oscillator used for these instructions was 10 MHz but there is an alternate mode for a 61 44 MHz oscillator as well If the bits become scrambled their original state may be recalled by choosing the appropriate mode If the internal divide by 2 DIV2 is enabled the VCO frequency will not change 13...

Page 14: ...y bit to view more information about what this does When the DIV2 bit is enabled the frequency from the part will be half of that shown on the PLL VCO tab The frequency on the PLL VCO tab does not reflect this because the divide by 2 is actually after the VCO Also be sure to load the device Ctrl L after changing this bit to allow the VCO to calibrate for optimal phase noise performance 14 ...

Page 15: ...N S The Registers tab shows the literal bits that are being sent to the part These are the registers every time the PLL is loaded by using the menu command or Ctrl L R5 INIT1 and R5 INIT 2 are just the R5 register being used to properly initialize the part So a single Ctrl L will load the part 15 ...

Page 16: ... S T R U C T I O N S The port setup tells CodeLoader what information goes where If this is wrong the part will not program Although LPT1 is usually correct CodeLoader does NOT automatically detect the correct port On some laptops it may be LPT3 Manual verification is required 16 ...

Page 17: ... C1 R2 C12 C2 VccVCO VccDIG VccPLL VccBUF R3 C3 C17 R4 C9 C4 R5 C5 OSCin VccVCO VccPLL VccBUF C13 C18 C20 R7 R23 R22 Ftest LD C15 C22 R1 R9 TRIGGE R GND 1 2 3 4 5 6 7 8 POWER C24 C14 C11 C19 C21 C23 Notethat AnyComponent w ithDesignator 100or Higheris ontheBottomSideof theBoard C10 VccDIG 1 NC 2 GND 3 NC 4 NC 5 VregBUF 6 NC 7 DATA 8 CLK 9 LE 10 CE 11 NC 12 NC 13 NC 14 NC 15 VccVCO 16 Vr egVCO 17 V...

Page 18: ...2 Panasonic P 22AHCT ND 603 10 0 1W Thick Film 0 22Ω R22 R23 10 2 Vishay CRCW06033R3JRT1 603 5 0 1W Thick Film 3 3Ω R1 R18 11 4 Vishay CRCW0603100JRT1 603 5 0 1W Thick Film 10Ω R2 R3 R4 R5 12 1 Vishay CRCW0603510JRT1 603 5 0 1W Thick Film 51Ω R6 13 1 Vishay CRCW0603102JRT1 603 5 0 1W Thick Film 1KΩ R2_LF 14 4 Vishay CRCW0603103JRT1 603 5 0 1W Thick Film 10KΩ R9 R11 R13 R15 15 4 Vishay CRCW0603123J...

Page 19: ...L M X 2 5 3 1 L Q 1 3 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Top Layer 19 ...

Page 20: ...L M X 2 5 3 1 L Q 1 3 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Mid Layer 1 Ground Plane 15 Mils Down FR4 20 ...

Page 21: ...L M X 2 5 3 1 L Q 1 3 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Mid Layer 2 Power 21 ...

Page 22: ...L M X 2 5 3 1 L Q 1 3 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bottom Layer Signal Note Total Board Thickness 61 mils 22 ...

Page 23: ...L M X 2 5 3 1 L Q 1 3 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Top Build Diagram 23 ...

Page 24: ...for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agre...

Page 25: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments LMX25311415EVAL NOPB ...

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