tracking will be directly proportional to the unbalance in the
quiescent output voltage. An optional potentiometer may be
placed at pin 1 as shown in
Figure 19 to null output offset.
The unbalanced current output for the circuit of
Figure 18 is
limited by the power dissipation of the package.
In the case of sustained unbalanced excess loads, the de-
vice will go into thermal limiting as the temperature sensing
circuit begins to function. For instantaneous high current
loads or short circuits the device limits the output current to
approximately 1.3 amperes until thermal shut-down takes
over or until the fault is removed.
HIGH INPUT IMPEDANCE CIRCUIT
The junction FET isolation circuit shown in
Figure 20 raises
the input impedance to 22 M
X
for low frequency input sig-
nals. The gate to drain capacitance (2 pF maximum for the
KE4221 shown) of the FET limits the input impedance as
frequency increases.
TL/H/7380 – 23
FIGURE 20
At 20 kHz the reactance of this capacitor is approximately
b
j4 M
X
giving a net input impedance magnitude of 3.9 M
X
.
The values chosen for R
1
, R
2
and C
1
provide an overall
circuit gain of at least 45 for the complete range of parame-
ters specified for the KE4221.
When using another FET device the relevant design equa-
tions are as follows:
A
V
e
#
R
1
R
1
a
1
g
m
J
(50)
(7)
g
m
e
g
m0
#
1
b
V
GS
V
p
J
(8)
V
GS
e
I
DS
R
1
(9)
I
DS
e
I
DSS
#
1
b
V
GS
V
P
J
2
(10)
The maximum value of R
2
is determined by the product of
the gate reverse leakage I
GSS
and R
2
. This voltage should
be 10 to 100 times smaller than V
P
. The output impedance
of the FET source follower is:
R
o
e
1
g
m
(11)
so that the determining resistance for the interstage RC
time constant is the input resistance of the LM380.
BOOSTED GAIN USING POSITIVE FEEDBACK
For applications requiring gains higher than the internally
set gain of 50, it is possible to apply positive feedback
around the LM380 for closed loopgains of up to 300.
Figure
21 shows a practical example of an LM380 in a gain of 200
circuit.
TL/H/7380 – 24
FIGURE 21. Boosted Gain of 200
Using Positive Feedback
The equation describing the closed loop gain is:
A
VCL
e
b
A
V(
0
)
1
b
A
V(
0
)
1
a
R
1
R
2
(12)
where A
V(
0
)
is complex at high frequencies but is nominally
the 40 to 60 specified on the data sheet for the pass band
of the amplifier. If 1
a
R
1
/R
2
approaches the value of
A
V(
0
)
, the denominator of equation 12 approaches zero, the
closed loop gain increases toward infinity, and the circuit
oscillates. This is the reason for limiting the closed loop gain
values to 300 or less.
Figure 22 shows the loaded and un-
loaded bode plot for the circuit shown in
Figure 21 .
TL/H/7380 – 25
FIGURE 22. Boosted Gain Bode Plot
The 24 pF capacitor C
2
shown on
Figure 21 was added to
give an overdamped square wave response under full load
conditions. It causes a high frequency roll-off of:
f
2
e
1
2
q
R
2
C
2
(13)
The circuit of
Figure 21 will have a very long (1000 sec) turn
on time if R
L
is not present, but only a 0.01 second turn on
time with an 8
X
load.
7
