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4.0 Functional Description
Table 1 describes the function of the various
jumpers on the ADC121S625B evaluation board.
The Evaluation Board schematic is shown in
Figure 2
.
Jumper
Pins 1 & 2
Pins 2 & 3
JP1
Select VA as the
VREF
Select 2.5V reg.
as the VREF
JP2
Short pins 1 & 2 and pins 3 & 4 to
bias input pins at VREF
JP3
Select
5P0V_REMOTE
from J5
Select 5P0V from
J1 (WV4S)
JP4
Enable OSC (not required)
JP5
Select on-board
clock OSC Y2
Select clock OSC
at BNC J6
Table 1 Jumper Functions
4.1 The Signal Input
The input signal to be digitized should be applied
across pins 1 & 3 of J2 or J3.
For input signals centered around ground, J2
should be utilized. Pin 2 of J2 is ground. Resistor
R4 is a terminating resistor for the input source.
Since all sources do not have the same output
impedance, R4 is not stuffed. However, it is
recommended that it is stuffed by the end user
with the appropriate value that matches the
source.
The DC biasing for inputs applied to J2 is supplied
through JP2. Short pins 1 & 2 and 3 & 4 of JP2 to
properly bias the input to VREF.
If it is desired to digitize a differential DC voltage
or a dynamic signal that is already properly biased
for the ADC121S625, apply the signal to be
digitized across pins 1 & 3 of J3. Pin 2 of J3 is
ground. When applying the input at J3, all shorts
on JP2 need to be removed.
Dynamic input signals should be applied through
a bandpass filter to eliminate the noise and
harmonics commonly associated with signal
sources. To accurately evaluate the performance
of the ADC121S625, the source must be better
than 90dB THD
4.2 ADC Reference Circuitry
This evaluation board includes the option of
selecting a fixed 2.5V shunt voltage reference or
VA as the reference voltage. Select the 2.5V
reference as VREF by shorting pins 2 & 3 of JP1
or select VA as VREF by shorting pins 1 & 2 of
JP1. If it is desirable to provide an external
reference voltage, the jumper must be removed
from JP1 and pin 2 may be driven directly.
If it is desirable to change the LM4040DIM3-2.5 to
an LM4040 with a different voltage, carefully
remove it and adjust the value of R3 to limit the
current through the LM4040.
4.3 ADC Clock Circuit
The crystal-based oscillator provided on the
evaluation board is selected by shorting pins 1 & 2
of JP5. It is best to remove any external signal
generator from J6 when using this oscillator to
reduce any unnecessary noise.
This board will also accept a clock signal from an
external source by connecting that source to BNC
J6 and shorting pins 2 & 3 of JP5. The input
applied at J6 is 50 ohm terminated by R14. The
external clock signal must meet TTL input
requirements. It is best to remove the oscillator at
Y2 when using an external clock source to reduce
any unnecessary noise.
Regardless of the clock source selected by JP5,
the clock signal is designed to be routed off the
ADC121S625B evaluation board to National’s
WV4 board. This assumes a “computer mode”
operation of the evaluation board. For applications
utilizing the evaluation board in manual mode,
short pins 4 & 10 of J4 with a short jumper wire to
provide the clock signal to the ADC121S625.
4.4 Digital Data Output
The serial data output from this board may be
monitored at J1 or J4.
4.5 Power Supply Connections
When operating in “computer mode” with the WV4
Board, voltage 5P0V for VA and 3P3V for U3
must be supplied to the ADC121S625B evaluation
board. For best performance from the
ADC121S625, the 5P0V voltage for VA should be
supplied by a separate power supply to J5. The
3P3V voltage may be pulled off the WV4 Board
with a jumper wire at TP10 (WV4) and applied to
TP5.
When operating in “manual mode”, only voltage
5P0V needs to be applied to J5.
The 5P0V voltage needs to be set b4.5V
and +5.5V and a shorting jumper must be placed
across pins 1 & 2 of JP3.
5.0 Software Operation and Settings
