TABLE 1. IRS Pin Functions
IRS Pin
Full-Scale Input
V
DDA
2.0V
P-P
V
SSA
1.5V
P-P
Floating
1.0V
P-P
1.8 OUTPUT PINS
The ADC10080 has 10 TTL/CMOS compatible Data Output
pins. The offset binary data is present at these outputs while
the DF and STBY pins are low. Be very careful when driving
a high capacitance bus. The more capacitance the output
drivers must charge for each conversion, the more instanta-
neous digital current flows through V
DDIO
and V
SSIO
. These
large charging current spikes can cause on-chip noise and
couple into the analog circuitry, degrading dynamic perfor-
mance. Adequate bypassing, limiting output capacitance and
careful attention to the ground plane will reduce this problem.
Additionally, bus capacitance beyond the specified
10 pF/pin will cause t
OD
to increase, making it difficult to prop-
erly latch the ADC output data. The result could be an appar-
ent reduction in dynamic performance. To minimize noise due
to output switching, minimize the load currents at the digital
outputs. This can be done by minimizing load capacitance
and by connecting buffers between the ADC outputs and any
other circuitry, which will isolate the outputs from trace and
other circuit capacitances and limit the output currents, which
could otherwise result in performance degradation. Only one
driven input should be connected to the ADC output pins.
1.9 APPLICATION SCHEMATICS
The following figures show simple examples of using the
ADC10080. Figure 5 shows a typical differentially driven in-
put. Figure 6 shows a single ended application circuit.
20048549
FIGURE 5. A Simple Application Using a Differential Driving Source
17
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ADC10080