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13
8.0 Hardware Schematic
Figure 10: ADC121C021 Evaluation Board Schematic
SC
L
_
EEP
R
O
M
S
D
A_
EEP
R
O
M
SC
L
SD
A
R5
0
1
1
VIA
8
1
1
TP
8
AG
N
D
1
1
VIA
9
C1
1
NS
VA
1
GND
2
VI
N
3
A
L
R
/ADR
4
SC
L
5
SD
A
6
U1 A
D
C1
21
C0
21
R1
3
NS
L2
100
uH
1
1
VIA
2
R4
NS
VDD
14
GND
7
OE
1
OU
T
8
Y1
O
S
C
(T
HRO
UG
H
-HO
LE
)
R1
7
NS
C1
2
0.
1u
F
C5
0.
1u
F
1
2
JP
3
I_
AM
P
R1
1
NS
1
1
VI
A3
C8
0.
1u
F
R1
6
56
2
4
6
8
10
12
14
1
3
5
7
9
11
13
J1
WV
4S
V
out
1
V(
-)
2
Vi
n
(+
)
3
Vi
n
(-
)
4
V(
+
)
5
U2 LM
P
773
1
C6
NS
1
1
TP
5
AG
N
D
1
2
JP
8
VA_
EX
T
_L
D
O
1
1
VIA
13
NS
1
2
3
6
7
8
4
5
U3
1
1
VI
A
12
R1
5
51
1
1
TP
3
AG
N
D
2
1
U5
LM
40
50
-4
.1
NC
1
GND
2
EN
3
Vi
n
4
Vr
ef
5
U6
N
S
(L
DO
Re
fe
re
nc
e)
JP
4
C1
0 O
hm
R
E
S
R1
4
NS
R9 2K
R3
NS
R8 2K
2
4
6
8
10
1
3
5
7
9
JP
5
1
1
TP
7
V
A
_EXT
L3
0 O
hm
R
1
2
JP
7
V
A
_EXT
_S
H
U
N
T
R1
2
0
1
1
VI
A6
C7
10.
0u
F
1
2
JP
2
V_
PU
LL
L1
100u
H
1
2
3
JP
1
IN
PU
T
SE
LE
C
T
1
1
TP
10
AG
N
D
1
1
VI
A5
R1
0
0
1
1
TP
6
AG
N
D
C4
0.
1u
F
R6
20
1
1
VI
A
10
R2
0
R1
9
51
1
2
3
JP
6
CL
K
S
E
LE
CT
R1
8
NS
2
3
4
5
1
J2
V_
IN
1
1
TP
9
V
A
_EXT
R1
NS
1
1
TP
2
AG
N
D
A0
1
A1
2
A2
3
GND
4
SDA
5
SCL
6
WP
7
VCC
8
U4
24
C
02
C3
10
.0
uF
1
1
VI
A
11
C1
0
0 O
hm
R
1
1
VI
A
1
C9
1.
0u
F
1
1
VI
A
4
1
1
VIA
7
R7
NS
C2
47
0p
F
3P
3V
_W
V
3P
3V
_W
V
5
P
0V
_W
V
3
P
3V
_W
V
3
P
3V
_W
V
3P
3V
_W
V
5P
0V
_W
V
VA
VA
VA
VA
5P
0V
_W
V
VA
VA
5
P
0V
_W
V
CL
K
S
E
N
D
5
P
0V
_W
V
3
P
3V
_W
V
CL
K
S
E
N
D
AG
N
D
VA
SE
LE
C
T
3P
3V
WV
4S
AG
N
D
V_
IN
2
1
V
_P
U
LL
SEL
EC
T
EEP
R
O
M
5P
0V
AG
N
D
A
DR1
A
DR0
AL
R
/A
D
R
AL
R
AG
N
D
V_
IN
SE
LE
C
T
S
m
al
l P
erf
-b
oa
rd
A
re
a
->
10
0 m
il i
nc
h s
pac
in
g
->
37
m
il in
ch
d
rills
->
57
m
il in
ch
p
ad
s
V+
_A
M
P
AG
N
D
AG
N
D
VA
_E
XT
4.
1V
S
H
U
N
T
3.
3V
L
D
O
R
E
FE
RE
NCE
RE
FE
R
E
NC
E
3
I2
C
SPI
VI
A
1
2
3
AG
N
D
AG
N
D
SD
A
---
SC
L
CS
b
SC
LK
SD
A
T
A
CL
K
S
E
LE
CT
WV
_C
LK
_I
N
A
G
N
D