![background image](http://html1.mh-extra.com/html/national-instruments/usb-6210/usb-6210_user-manual_3656406051.webp)
Chapter 4
Analog Input
©
National Instruments Corporation
4-15
software or hardware can stop it once a finite acq
u
isition completes. When
u
sing an internally generated AI Sample Clock, yo
u
also can specify a
config
u
rable delay from AI Start Trigger to the first AI Sample Clock p
u
lse.
By defa
u
lt, this delay is set to two ticks of the AI Sample Clock Timebase
signal. When
u
sing an externally generated AI Sample Clock, yo
u
m
u
st
ens
u
re the clock signal is consistent with respect to the timing req
u
irements
of AI Convert Clock. Fail
u
re to do so may res
u
lt in AI Sample Clock p
u
lses
that are masked off and acq
u
isitions with erratic sampling intervals. Refer
to the
section for more information abo
u
t the
timing req
u
irements between AI Convert Clock and AI Sample Clock.
Fig
u
re 4-8 shows the relationship of AI Sample Clock to AI Start Trigger.
Figure 4-8.
AI Sample Clock and AI Start Trigger
AI Sample Clock Timebase Signal
Yo
u
can ro
u
te any of the following signals to be the AI Sample Clock
Timebase (ai/SampleClockTimebase) signal:
•
20 MHz Timebase
•
100 kHz Timebase
•
(USB-6210/6211/6215 Devices)
PFI <0..3>
•
(USB-6212/6216 Devices)
PFI <0..15>
•
(USB-6218 Devices)
PFI <0..3>, PFI <8..11>
AI Sample Clock Timebase is not available as an o
u
tp
u
t on the I/O
connector. AI Sample Clock Timebase is divided down to provide one of
the possible so
u
rces for AI Sample Clock. Yo
u
can config
u
re the polarity
selection for AI Sample Clock Timebase as either rising or falling edge.
AI
Sa
mple Clock Time
bas
e
AI
S
t
a
rt Trigger
AI
Sa
mple Clock
Del
a
y
From
S
t
a
rt
Trigger