Chapter 8
Counters
©
National Instruments Corporation
8-27
freq
u
ency of the system. Fig
u
re 8-29 shows an example of p
u
lse generation
for ETS; the delay from the trigger to the p
u
lse increases after each
s
u
bseq
u
ent Gate active edge.
Figure 8-29.
Pulse Generation for ETS
For information abo
u
t connecting co
u
nter signals, refer to the
section.
Counter Timing Signals
USB-621
x
devices feat
u
re the following co
u
nter timing signals:
•
•
•
•
•
•
•
•
•
Counter n Internal Output Signal
•
•
In this section,
n
refers to either Co
u
nter 0 or 1. For example, Co
u
nter
n
So
u
rce refers to two signals—Co
u
nter 0 So
u
rce (the so
u
rce inp
u
t to
Co
u
nter 0) and Co
u
nter 1 So
u
rce (the so
u
rce inp
u
t to Co
u
nter 1).
OUT
D1
D2 = D1 +
Δ
D D
3
= D1 + 2
Δ
D
GATE
