Figure 2.
NI 5665 3.6 GHz VSA Slave Module Placement
NI PXIe-1075
18
17
16
15
13
12
10
9
8
7
6
5
4
3
2
1
H
H
H
H
14
H
H
H
H
11
ESD
SENSITIVE
ACCESS ACTIVE
LO3
800 MHz
LO2
4 GHz
LO1
3.2 GHz - 8.3 GHz
OUT
ALL PORTS
50
Ω
NI PXIe-5653
Synthesizer
REF IN
10 MHz
5 V p-p MAX
REF OUT
10 MHz
1.5 V p-p MAX
REF OUT
100 MHz
1.5 V p-p MAX
ESD
SENSITIVE
ACCESS
ACTIVE
OUT
IN
LO3
LO2
LO1
ALL PORTS
50
Ω
NI PXIe-5603
Downconverter 20 Hz - 3.6 GHz
RF IN
0 V DC, DC COUPLED
25 V DC MAX, AC COUPLED
+20 dBm MAX > 10 MHz
0 dBm MAX < 10 MHz
IF OUT
+22 dBm MAX
0 V DC
+15 dBm MAX
25 V DC MAX
+15 dBm MAX
0 V DC
ACCESS
ACTIVE
CLK IN
CLK OUT
PFI 1
ESD
SENSITIVE
TTL
6.3 Vp-p
MAX
2 Vp-p
NOM
+20 dBm MAX
50
Ω
50
Ω
50
Ω
NI PXIe-5622
16-Bit IF Digitizer
IF IN
ESD
SENSITIVE
ACCESS
ACTIVE
OUT
IN
LO3
LO2
LO1
ALL PORTS
50
Ω
NI PXIe-5603
Downconverter 20 Hz - 3.6 GHz
RF IN
0 V DC, DC COUPLED
25 V DC MAX, AC COUPLED
+20 dBm MAX > 10 MHz
0 dBm MAX < 10 MHz
IF OUT
+22 dBm MAX
0 V DC
+15 dBm MAX
25 V DC MAX
+15 dBm MAX
0 V DC
ACCESS
ACTIVE
CLK IN
CLK OUT
PFI 1
ESD
SENSITIVE
TTL
6.3 Vp-p
MAX
2 Vp-p
NOM
+20 dBm MAX
50
Ω
50
Ω
50
Ω
NI PXIe-5622
16-Bit IF Digitizer
IF IN
ESD
SENSITIVE
ACCESS
ACTIVE
OUT
IN
LO3
LO2
LO1
ALL PORTS
50
Ω
NI PXIe-5603
Downconverter 20 Hz - 3.6 GHz
RF IN
0 V DC, DC COUPLED
25 V DC MAX, AC COUPLED
+20 dBm MAX > 10 MHz
0 dBm MAX < 10 MHz
IF OUT
+22 dBm MAX
0 V DC
+15 dBm MAX
25 V DC MAX
+15 dBm MAX
0 V DC
ACCESS
ACTIVE
CLK IN
CLK OUT
PFI 1
ESD
SENSITIVE
TTL
6.3 Vp-p
MAX
2 Vp-p
NOM
+20 dBm MAX
50
Ω
50
Ω
50
Ω
NI PXIe-5622
16-Bit IF Digitizer
IF IN
ESD
SENSITIVE
ACCESS
ACTIVE
OUT
IN
LO3
LO2
LO1
ALL PORTS
50
Ω
NI PXIe-5603
Downconverter 20 Hz - 3.6 GHz
RF IN
0 V DC, DC COUPLED
25 V DC MAX, AC COUPLED
+20 dBm MAX > 10 MHz
0 dBm MAX < 10 MHz
IF OUT
+22 dBm MAX
0 V DC
+15 dBm MAX
25 V DC MAX
+15 dBm MAX
0 V DC
ACCESS
ACTIVE
CLK IN
CLK OUT
PFI 1
ESD
SENSITIVE
TTL
6.3 Vp-p
MAX
2 Vp-p
NOM
+20 dBm MAX
50
Ω
50
Ω
50
Ω
NI PXIe-5622
16-Bit IF Digitizer
IF IN
2
2
2
1
1. Master NI 5665 3.6 GHz VSA
2. Slave NI 5665 3.6 GHz VSA
Interconnecting the Modules
This section describes how to interconnect the master NI 5665 modules and how to connect
the slave NI 5665 modules to the master NI 5665 modules.
Note
This module configuration frequency-locks to the NI 5653 100 MHz onboard
Reference Clock by daisy chaining the 100 MHz Reference Clock to slave digitizer
modules. To frequency-lock to the PXI backplane, the NI 5653 requires an OCXO-
quality timebase source present on the PXI backplane.
For the best long-term phase stability over temperature, use the PXI backplane as the
Reference Clock source, but override the native PXI chassis backplane clock with an
OCXO-quality timebase that meets the requirements listed in the
NI PXIe-5665
Specifications
. The NI 5665 cannot lock to the native PXI chassis backplane clock,
and attempting to do so without overriding it with an OCXO timebase results in
phase-locked loop (PLL) lock errors. The NI PXIe-6674T Timing and Multichassis
Synchronization module is an option for synchronizing multiple digitizer clocks.
The NI 6674T 10 MHz clock can be driven onto the PXI backplane when placed in
the chassis System Timing Slot, also known as the Star Trigger Controller Slot. You
can also connect the output of the NI 6674T 10 MHz clock to the 10 MHz BNC IN
terminal on the back of the PXI chassis from any PXI chassis slot using an SMA-to-
BNC cable.
NI PXIe-5665 3.6 GHz Vector Signal Analyzer MIMO Platform Getting Started Guide
|
© National Instruments
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3
Summary of Contents for PXIe-5603
Page 1: ...PXIe 5653...
