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Chapter 1
Getting Started
An independent buffer (having a source impedance matched to the backplane and a skew of less
than 250 ps between slots) drives PXI_CLK10 to each peripheral slot. You can use this common
reference clock signal to synchronize multiple modules in a measurement or control system.
An independent buffer drives PXIe_CLK100 to each peripheral slot. These clocks are matched
in skew to less than 100 ps. The differential pair must be terminated on the peripheral with
LVPECL termination for the buffer to drive PXIe_CLK100 so that when there is no peripheral
or a peripheral that does not connect to PXIe_CLK100, there is no clock being driven on the pair
to that slot. Refer to Figure 1-6 for a termination example.
Figure 1-6.
CLK100 Termination
An independent buffer drives PXIe_SYNC100 to each peripheral slot. The differential pair must
be terminated on the peripheral with LVPECL termination for the buffer to drive
PXIe_SYNC100 so that when there is no peripheral or a peripheral that does not connect to
PXIe_SYNC100, there is no SYNC100 signal being driven on the pair to that slot. Refer to
Figure 1-6 for a termination example.
PXI_CLK10, PXIE_CLK100, and PXIE_SYNC100 are driven to every peripheral slot and have
the default timing relationship described in Figure 1-7.
Figure 1-7.
System Reference Clock Default Behavior
CLK100 –
50
Ω
50
Ω
47
Ω
0.01 µF
+
–
PXIe_CLK100
PXI_CLK10
PXIe_
S
YNC100
0 1 2
3
4 5 6 7
8
9 0 1 2
3
4 5 6 7
8
9 0 1 2
3
4 5 6 7
8
9