Chapter 1
Introduction
©
National Instruments Corporation
1-5
R Series Multifunction RIO User Manual
Reconfigurable I/O Architecture
Fig
u
re 1-1 shows an FPGA connected to fixed I/O reso
u
rces and a b
u
s
interface. The fixed I/O reso
u
rces incl
u
de A/D converters (ADCs),
D/A converters (DACs), and digital I/O lines.
Figure 1-1.
High-Level FPGA Functional Overview
Software accesses the R Series device thro
u
gh the b
u
s interface, and the
FPGA connects the b
u
s interface and the fixed I/O to make possible timing,
triggering, processing, and c
u
stom I/O meas
u
rements
u
sing the LabVIEW
FPGA Mod
u
le.
The FPGA logic provides timing, triggering, processing, and c
u
stom I/O
meas
u
rements. Each fixed I/O reso
u
rce
u
sed by the application
u
ses a small
portion of the FPGA logic that controls the fixed I/O reso
u
rce. The b
u
s
interface also
u
ses a small portion of the FPGA logic to provide software
access to the device.
The remaining FPGA logic is available for higher-level f
u
nctions s
u
ch as
timing, triggering, and co
u
nting. The f
u
nctions
u
se varied amo
u
nts of logic.
Yo
u
can place
u
sef
u
l applications in the FPGA. How m
u
ch FPGA space
yo
u
r application req
u
ires depends on yo
u
r need for I/O recovery, I/O, and
logic algorithms.
FPGA
Bus Interface
Fixed I/O Resource
Fixed I/O Resource
Fixed I/O Resource
Fixed I/O Resource
Summary of Contents for PXI-7842
Page 1: ...PXI 7842...
