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3-7
NI PXI-6683 Series User Manual
Table 3-5 outlines the function and direction of the signals discussed in detail in the remainder
of this chapter. These signals are also identified in Figure 3-2.
Table 3-5.
NI PXI-6683 Series I/O Terminals
Signal Name
Direction
Description
PXI_CLK10_IN
(System Timing Slot
Only)
(Not in NI PXI-6683H)
Out
This is a signal that can replace the native
10 MHz oscillator on the PXI backplane.
PXI_CLK10_IN may originate from the onboard
TCXO or from an external source connected to
CLKIN.
PXI_CLK10
In
This signal is the PXI 10 MHz backplane clock.
By default, this signal is the output of the native
10 MHz oscillator in the chassis. An
NI PXI-6683 Series in the system timing slot can
replace this signal with PXI_CLK10_IN.
Oscillator
N/A
This is the output of the 10 MHz TCXO. It is used
by the FPGA for synchronization. An
NI PXI-6683 in the system timing slot can be
routed to CLKOUT or PXI_CLK10_IN. The
TCXO is a very stable and accurate frequency
source.
CLKIN
(Not in NI PXI-6683H)
In
CLKIN is a signal connected to the SMB input
pin of the same name. An NI PXI-6683 in the
system timing slot can route CLKIN to
PXI_CLK10_IN.
CLKOUT
Out
CLKOUT is the signal on the SMB output pin
of the same name. Either the oscillator (TCXO)
or PXI_CLK10 may be routed to this output.
PXI_STAR<0..12>
(Not in NI PXI-6683H)
In/Out
The PXI star trigger bus connects the system
timing slot to Slot <3..15> in a star configuration.
The electrical paths of each star line are closely
matched to minimize intermodule skew. An
NI PXI-6683 in the system timing slot can route
signals to Slots <3..15> using the star trigger bus.
