Table 3. Available Pins on the DIO connector.
Signal
Type
Direction
MGT Tx± <0..3>
Xilinx UltraScale GTH
Output
MGT Rx± <0..3>
Xilinx UltraScale GTH
Input
DIO <0..7>
Single-ended
Bidirectional
5.0 V
DC
Output
GND
Ground
—
Figure 5. QSFP+ Connector Pinout
GND
Rx2n
Rx2p
GND
Rx4n
Rx4p
ModPrsL
GND
IntL
Vcc Tx
GND
Rx1n
Rx1p
GND
Rx3n
Rx3p
SDA
GND
SCL
Vcc Rx
19
18
17
16
15
14
13
12
11
29
10
20
21
22
23
24
25
26
27
28
9
8
7
6
5
4
3
2
1
30
31
32
33
34
35
36
37
38
Vcc1
LPMode
GND
Tx3p
Tx3n
GND
Tx1p
Tx1n
GND
ResetL
ModSelL
GND
Tx4p
Rx4n
GND
Tx2p
Tx2n
GND
Table 4. Available Pins on the QSFP+ Connectors
Pin
Symbol
Name/Description
1
GND
Ground
2
Tx2n
Transmitter Inverted Data Input
3
Tx2p
Transmitter Non-Inverted Data Input
4
GND
Ground
5
Tx4n
Transmitter Inverted Data Input
6
Tx4p
Transmitter Non-Inverted Data Input
8
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PCIe-6593 Getting Started Guide
