The following figure shows a block diagram of the carrier portion of the PCIe-5775 (KU040
and KU060 FPGA versions).
Figure 5. Carrier Block Diagram (KU040 and KU060)
DIO Connector
(Front Panel)
Adapter Module
Connector
+5 V
+1.8 V
+12 V
GPIO
Configuration, GPIO
MGTs
Reference Clock
Power Supplies
Flash
FPGA
Triggers
Clk 100
Gen3 x8 PCIe
+12 V, +3.3 V
+12 V
Clk 10
Module Clocking
Synchronization
PLL
DRAM Bank 0
(2 GB)
DRAM Bank 1
(2 GB)
Synchronization
Connector
PCIe
Connectors
MGTs
The following figure shows a block diagram of the I/O portion of the PCIe-5775.
Figure 6. PCIe-5775 Block Diagram
EXTERNAL REF/SCLK
CLK IN SMA
AI1 SMA
ADC12DJ3200
Dual 12-bit, 3.2 GS/s
Single 12-bit, 6.4 GS/s
AI0 SMA
ANALOG INPUT
AC (Balun)
Coupled Path
AC (Balun)
Coupled Path
Adapter Module
Connector
CLOCKING
10
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PCIe-5775 Getting Started Guide
