Appendix B
Register-Level Programming — Register Map and Description
PCI-DIO-96/PXI-6508/PCI-6503 User Manual
B-4
ni.com
Register Map and Description
This section describes in detail the address and function of each PCI-DIO-96, PXI-6508, and
PCI-6503 register.
Introduction
The three 8-bit ports of the 82C55A are divided into two groups of 12 signals: group A and
group B. One 8-bit control word selects the mode of operation for each group. The group A
control bits configure port A (A<7..0>) and the upper 4 bits (nibble) of port C (C<7..4>). The
group B control bits configure port B (B<7..0>) and the lower nibble of port C (C<3..0>).
These configuration bits are defined in the
Register Description for the 82C55A
section.
When differentiation is required between the four 82C55A PPI devices on the PCI-DIO-96
and PXI-6508, they are referenced as PPI A, PPI B, PPI C, and PPI D.
On the PCI-DIO-96 and PXI-6508, the three 16-bit counters of the 82C53 are accessed
through individual data ports and controlled by one 8-bit control word. The control word
selects how the counter data ports are accessed and what mode the counter uses. The
Description for the 82C53 (PCI-DIO-96, PXI-6508 Only)
section contains definitions for
these configuration bits.
In addition to the 82C55A and 82C53 devices, there are two registers that select which
onboard signals are capable of generating interrupts. There are two interrupt signals from
each of the 82C55A devices and two interrupt signals from the 82C53 device. Individual
enable bits select which of these 10 signals can generate interrupts. Also, a master enable
signal determines whether the board can actually send a request to the computer. The
Description for the Interrupt Control Registers
section contains definitions for the
configuration bits for these registers.
