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National Instruments PC-LPM-16/PnP, User Manual

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National Instruments PC-LPM-16/PnP User Manual Download Page 94

Appendix D     Register-Level Programming

PC-LPM-16/PnP User Manual

D-22

 National Instruments Corporation

Counter Mode Register

(Continued)

5–4

RL<1..0>

Read/Write Select Bits—These bits select data written 
to or read from a counter, or these bits send a Counter 
Latch command.

The Counter Latch command latches the current count 
of the register selected by SC1 and SC0. The next read 
from the selected counter returns the latched data.

RL1

RL0

Operation

0

0

Counter Latch command

0

1

Read and write least significant 
byte only

1

0

Read and write most significant 
byte only

1

1

Read and write least significant 
byte then most significant byte

a.Book : l.Appendix D  Page 22  Wednesday, November 20, 1996  6:36 PM

Summary of Contents for PC-LPM-16/PnP

Page 1: ...r Manual Multifunction I O Board for the PC November 1996 Edition Part Number 320287C 01 Copyright 1990 1996 National Instruments Corporation All Rights Reserved a Book a Title Page 1 Wednesday November 20 1996 6 36 PM ...

Page 2: ...527 2321 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 5734815 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 520 2635 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 Taiwan 02 377 1200 U K 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin ...

Page 3: ...L OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due ...

Page 4: ...bVIEW and LabWindows CVI Application Software 1 2 NI DAQ Driver Software 1 3 Register Level Programming 1 4 Optional Equipment 1 5 Custom Cables 1 5 Unpacking 1 6 Chapter 2 Installation and Configuration Hardware Installation 2 1 Software Installation 2 2 Board Configuration 2 2 Plug and Play 2 2 Base I O Address and Interrupt Selection 2 3 Non Plug and Play 2 3 Chapter 3 Theory of Operation Funct...

Page 5: ...tion Descriptions 4 3 Analog Input Signal Connections 4 5 Connections for Signal Sources 4 5 Digital I O Signal Connections 4 6 Power Connections 4 7 Power Rating 4 8 Timing Connections 4 8 Data Acquisition Timing Connections 4 8 General Purpose Timing Signal Connections and General Purpose Counter Timing Signals 4 9 Appendix A Specifications Appendix B MSM82C53 Data Sheet Appendix C Using Your PC...

Page 6: ...ignal Connections 4 6 Figure 4 3 Analog Input Signal Connections 4 7 Figure 4 4 EXTCONV Signal Timing 4 9 Figure 4 5 Event Counting Application with External Switch Gating 4 10 Figure 4 6 Frequency Measurement Application 4 11 Figure 4 7 General Purpose Timing Signals 4 12 Figure A 1 ADC Errors A 6 Figure C 1 PC LPM 16 Parts Locator Diagram C 5 Figure C 2 Example Base I O Address Switch Settings C...

Page 7: ...cs C 1 Table C 2 PC Bus Interface Factory Settings C 7 Table C 3 Switch Settings with Corresponding Base I O Address and Base I O Address Space C 9 Table D 1 PC LPM 16 PnP Register Map D 1 Table D 2 Unipolar Input Mode A D Conversion Values D 29 Table D 3 Bipolar Input Mode A D Conversion Values D 30 a Book c Table of Contents Page viii Wednesday November 20 1996 6 36 PM ...

Page 8: ...ows Chapter 1 Introduction describes the PC LPM 16 PnP lists what you need to get started software programming choices and optional equipment and explains how to unpack the PC LPM 16 PnP Chapter 2 Installation and Configuration describes the installation and configuration of the PC LPM 16PnP Chapter 3 Theory of Operation includes an overview of the PC LPM 16PnP board and explains the operation of ...

Page 9: ...nd Conventions Used in This Manual The following conventions are used in this manual Angle brackets containing numbers separated by an ellipsis represent a range signal or port for example ACH 0 7 stands for ACH0 through ACH7 bold Bold text denotes menus menu items or dialog box buttons or options and error messages bold italic Bold italic text denotes a note caution or warning italic Italic text ...

Page 10: ... interrupt level Plug and Play systems automatically arbitrate and assign system resources to a PnP product Abbreviations acronyms metric prefixes mnemonics symbols and terms are listed in the Glossary National Instruments Documentation The PC LPM 16 PnP User Manual is one piece of the documentation set for your DAQ or SCXI system You could have any of several types of manuals depending on the har...

Page 11: ... and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you are making your connections SCXI Chassis User Manual If you are using SCXI read this manual for maintenance information on the chassis and for installation instructions Related Documentation The following document contains information that you may find help...

Page 12: ... for laboratory work in industrial and academic environments The board s low power consumption and small size make the PC LPM 16 PnP especially suitable for laptop computers The multichannel analog input is useful in signal analysis and data logging The 12 bit ADC is useful in high resolution applications such as chromatography temperature measurement and DC voltage measurement You can use the 16 ...

Page 13: ...ition and control applications LabVIEW uses graphical programming whereas LabWindows CVI enhances traditional programming languages Both packages include extensive libraries for data acquisition instrument control data analysis and graphical data presentation LabVIEW features interactive graphics a state of the art user interface and a powerful graphical programming language The LabVIEW Data Acqui...

Page 14: ...SCXI RTSI calibration messaging and acquiring data to extended memory NI DAQ has both high level DAQ I O functions for maximum ease of use and low level DAQ I O functions for maximum flexibility and performance Examples of high level functions are streaming data to disk or acquiring a certain number of data points An example of a low level function is writing directly to registers on the DAQ devic...

Page 15: ...mmended for most users Even if you are an experienced register level programmer consider using NI DAQ LabVIEW or LabWindows CVI to program your National Instruments DAQ hardware Using the NI DAQ LabVIEW or LabWindows CVI software is as easy and as flexible as register level programming and can save weeks of development time LabWindows CVI PC or Sun SPARCstation LabVIEW PC Macintosh or Sun SPARCsta...

Page 16: ...e or call the office nearest you Custom Cables National Instruments currently offers a cable termination accessory the CB 50 for use with the PC LPM 16 PnP This kit includes a terminated 50 conductor flat ribbon cable and a connector block Signal input and output wires can be attached to screw terminals on the connector block and connected to the PC LPM 16 PnP I O connector The CB 50 is useful for...

Page 17: ...ision 3M part number 3365 50 T B Ansley Corporation part number 171 50 Unpacking Your PC LPM 16 PnP board is shipped in an antistatic package to prevent electrostatic damage to the board Electrostatic discharge can damage several components on the board To avoid such damage in handling the board take the following precautions Ground yourself via a grounding strap or by holding a grounded object To...

Page 18: ...llation instructions but consult your computer user manual or technical reference manual for specific instructions and warnings 1 Turn off and unplug your computer 2 Remove the top cover or access port to the I O channel 3 Remove the expansion slot cover on the back panel of the computer 4 Insert the PC LPM 16PnP board into any 8 bit or 16 bit slot It may be a tight fit but do not force the board ...

Page 19: ...to Appendix D Register Level Programming for software configuration information Board Configuration Plug and Play The PC LPM 16PnP is fully compatible with the industry standard Intel Microsoft Plug and Play Specification version 1 0a A Plug and Play system arbitrates and assigns resources through software freeing you from manually setting switches and jumpers These resources include the board bas...

Page 20: ...cate resources but these can be changed in the Device Manager a Click the right mouse button on My Computer to bring up system properties b Select Device Manager c Select Data Acquisition Devices d Select the PC LPM 16 You can change address and interrupt settings on the Resources page For Windows 3 10 or 3 11 you can use the NI DAQ Configuration Utility formerly WDAQCONF to assign the board resou...

Page 21: ...ing up the PC LPM 16PnP PC I O channel interface circuitry Analog input and data acquisition circuitry Digital I O circuitry Timing I O circuitry You can execute data acquisition functions by using the analog input circuitry and some of the timing I O circuitry The internal data and control buses interconnect the components The theory of operation for each of these components is explained in the r...

Page 22: ...ace Plug and Play 1 MHz Interrupt Interface 256 Word FIFO MSM82C53 Digital I O 12 Bit Sampling ADC Input Mux 16 Channel Single Ended 16 8 8 3 Buffer A D Timing Scanning Counter EXTCONV GATE 0 2 CLK 1 2 CLK0 OUT0 OUT 0 2 OUT1 OUT1 EXTINT FROM A D FIFO 0 5 A 1 0 A 12 V 12 V 12 V 5 V 12 V 5 V I O Connector 2 3 a Book g chapter 3 Page 2 Wednesday November 20 1996 6 36 PM ...

Page 23: ...try monitors address lines SA4 through SA15 to generate the board enable signal and uses lines SA0 through SA3 plus timing signals to generate the onboard register select signals and read write signals The data buffers control the direction of data transfer on the bidirectional data lines based on whether the transfer is a read or write operation The interrupt control circuitry routes any enabled ...

Page 24: ... bit of the Command Register 1 description in Appendix D Register Level Programming Analog Input and Data Acquisition Circuitry The PC LPM 16PnP has 16 channels of analog input with 12 bit A D conversion Using the timing circuitry the PC LPM 16PnP can also automatically time multiple A D conversions Figure 3 3 shows a block diagram of the analog input and data acquisition circuitry Figure 3 3 Anal...

Page 25: ... D FIFO saves the value for later reading and the ADC can start a new conversion Secondly the A D FIFO can collect up to 256 A D conversion values before losing any information thus giving the software some extra time 256 times the sample interval to catch up with the hardware If the A D FIFO stores more than 256 values without the A D FIFO being read an error condition called A D FIFO Overflow oc...

Page 26: ...isition operation Data acquisition timing consists of signals that initiate a data acquisition operation and generate scanning clocks Sources for these signals are supplied mainly by timers on the PC LPM 16PnP board One of the three counters of the onboard MSM82C53 is reserved for this purpose You can initiate an A D conversion by a falling edge on the counter 0 output OUT0 of the MSM82C53 onboard...

Page 27: ...ack and hold stage During multichannel scanning the settling time of the input multiplexers and operational amplifier further limits the data acquisition rate After the input multiplexers switch channels the amplifier must be able to settle to the new input signal value to within 12 bit accuracy before performing an A D conversion or else it will not achieve 12 bit accuracy The maximum data acquis...

Page 28: ...utput Register respectively Reading the Digital Input Register returns the current state of the DIN 0 7 lines Writing to the Digital Output Register drives the new value onto the DOUT 0 7 lines The external device may drive the EXTINT signal to indicate the readiness of data transfer Figure 3 4 Digital I O Circuitry Block Diagram PC I O Channel 8 8 I O Connector EXTINT 8 8 I O RD I O WR DIN 0 7 DO...

Page 29: ...ounter 0 for data acquisition timing and counters 1 and 2 are free for general use You can program all three counter timers to operate in several useful timing modes The programming and operation of the MSM82C53 is presented in detail both in Appendix B MSM82C53 Data Sheet and Appendix D Register Level Programming The timebase for counter 0 uses a 1 MHz clock generated from an onboard oscillator Y...

Page 30: ... counter has a clock input pin a gate input pin and an output pin labeled CLK GATE and OUT respectively The MSM82C53 counters are numbered zero through two and their GATE CLK and OUT pins are labeled GATEN CLKN and OUTN where N is the counter number Counter CLK GATE OUT a Book g chapter 3 Page 10 Wednesday November 20 1996 6 36 PM ...

Page 31: ...of your computer after you have properly installed the board Installation instructions are in Chapter 2 Installation and Configuration Warning Connections that exceed any of the maximum ratings of input or output signals on the PC LPM 16PnP can damage the board and the computer This includes connecting any power signals to ground and vice versa Each signal description in this section includes info...

Page 32: ...5 DIN3 DIN1 12 V DGND ACH7 ACH6 ACH5 ACH4 ACH3 ACH2 ACH1 ACH0 AIGND DGND OUT2 GA TE1 EXTCONV OUT1 DOUT6 DOUT4 CLK2 GA TE0 DOUT2 DOUT0 DIN6 DIN4 DIN2 DIN0 12 V ACH15 ACH14 ACH13 ACH12 ACH11 ACH10 ACH9 ACH8 AIGND 49 50 47 48 45 46 43 44 41 42 39 40 37 38 35 36 33 34 31 32 29 30 27 28 25 26 23 24 21 22 19 20 17 18 15 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 a Book h chapter 4 Page 2 Wednesday November 20 ...

Page 33: ... as well as the 5 VDC supply 20 12 V DGND 12 VDC Power Supply Output Pin The maximum current is 5 0 mA 21 12 V DGND 12 VDC Power Supply from the Computer Bus This power line has a 0 5 A self resetting fuse in series 22 29 DIN 0 7 DGND Digital Input Data Lines These signals are TTL compatible digital input lines DIN7 is the MSB DIN0 the LSB 30 37 DOUT 0 7 DGND Digital Output Data Lines These signal...

Page 34: ... restarting of counter 1 45 CLK1 DGND Counter 1 Clock Input This pin is the clock input for counter 1 46 OUT2 DGND Counter 2 Output This pin is the output of counter 2 47 GATE2 DGND Counter 2 Gate Input This signal controls the starting interruption and restarting of counter 2 48 CLK2 DGND Counter 2 Clock Input This pin is the clock input for counter 2 49 5 V DGND 5 Volts This is the 5 VDC power s...

Page 35: ... You can only use this pin to cause conversions not as a monitor to detect conversions caused by the onboard sample interval timer Refer to Figure 4 4 for more information about EXTCONV timing The following input ranges and maximum ratings apply to inputs ACH 0 15 Input signal range Bipolar input 5 V or 2 5 V Unipolar input 0 to 10 V or 0 to 5 V Maximum input voltage rating 45 V powered on 35 V po...

Page 36: ...um 7 0 V with respect to DGND voltage input rating 0 5 V with respect to DGND Digital input compatibility TTL compatible Input current high or low level 10 µA Digital output compatibility TTL compatible Output current source capability 8 mA at VOH 2 7 V Output current sink capability 6 mA at VOL 0 5 V VM ACH 0 15 Input Multiplexer Operational Amplifier I O Connector 3 4 5 18 1 2 PC LPM 16PnP AIGND...

Page 37: ...lies 5 V from the computer I O channel power supply Pin 20 of the I O connector supplies 12 V from the computer I O channel power supply The 12 V is supplied from the computer I O power supply with a resistor in series These pins are referenced to DGND and can be used to power external digital circuitry The 5 V supply at the I O connector has a 1 0 A protection fuse in series The 12 V supply at th...

Page 38: ... are explained in the General Purpose Timing Signal Connections and General Purpose Counter Timing Signals section later in this chapter Data Acquisition Timing Connections Counter 0 on the MSM82C53 counter timer is used as a sample interval counter in timed A D conversions In addition to counter 0 EXTCONV can externally time conversions See Appendix D Register Level Programming for the programmin...

Page 39: ...erations The single exception is counter 0 which has an internal 1 MHz clock Chapter 3 Theory of Operation briefly describes the MSM82C53 counter timer For detailed information on this counter timer see Appendix B MSM82C53 Data Sheet For pulse and square wave generation program a counter to generate a timing signal at its OUT output pin For event counting program a counter to count the rising or f...

Page 40: ...a counter to be edge gated Apply an edge to the counter GATE input to start the counter You can program the counter to start counting after receiving a low to high edge The time lapse since receiving the edge equals the counter value difference loaded value minus read value multiplied by the CLK period For frequency measurement program a counter to be level gated and count the number of falling ed...

Page 41: ... counter to generate the gate signal in this application Figure 4 6 Frequency Measurement Application 4 7 kΩ resistors pull up the GATE and CLK pins to 5 V Figure 4 7 shows the timing requirements for the GATE and CLK input signals and the timing specifications for the OUT output signals The following specifications and ratings apply to the MSM82C53 I O signals Absolute maximum voltage input ratin...

Page 42: ...t VOH 1 0 mA max IOL output sink current at VOL 4 0 mA max Figure 4 7 General Purpose Timing Signals The GATE and OUT signals in Figure 4 7 are referenced to the rising edge of the CLK signal toutc tgwl tgwh tsc VIH VIL VIH VIL VOH VOL tpwh tpwl tgh tgsu toutg tsc clock period 125 ns min tpwh clock high level 60 ns min tpwl clock lowlevel 60 ns min tgsu gate setup time 60 ns min tgh gate hold time...

Page 43: ... rate 50 kS s Input signal ranges 5 V 2 5 V 0 to 10 V or 0 to 5 V software selectable Input coupling DC Overvoltage protection 45 V powered on 35 V powered off Inputs protected ACH 0 15 FIFO buffer size 256 S Data transfers Interrupts programmed I O Transfer Characteristics Relative accuracy 1 0 LSB typ 1 5 LSB max Integral nonlinearity 0 5 LSB max Differential nonlinearity 1 0 LSB max For more in...

Page 44: ...acteristics Input impedance 0 1 GΩ in parallel with 40 pF typ Dynamic Characteristics Bandwidth Gain 3 dB 200 kHz typ Settling time to 1 0 LSB for full scale step 20 µs max at all ranges System noise 0 1 LSB rms for all ranges Stability Recommended warm up time 15 min Onboard calibration reference Level 5 000 V 2 5 mV Temperature coefficient 20 ppm C max Long term stability 15 ppm typ Digital I O ...

Page 45: ...urrent 4 0 mA 0 45 V max Output logic high voltage at output current 1 0 mA 3 7 V min Base clocks available 1 MHz 0 01 Max source frequency 8 MHz Min source pulse duration 60 ns Min gate pulse duration 50 ns Data transfers Programmed I O Digital logic levels Level Minimum Maximum Input low voltage 0 V 0 8 V Input high voltage 2 V 5 0 V Input low current Vin 0 V 10 µA Input high current Vin 5 V 10 ...

Page 46: ... deviation from a straight line for the analog input to digital output transfer curve If a ADC has been calibrated perfectly then this straight line is the ideal transfer function and the relative accuracy specification indicates the worst deviation from the ideal that the ADC permits A relative accuracy specification of 1 LSB is roughly equivalent to but not the same as a 1 2 LSB nonlinearity or ...

Page 47: ...e range of analog values that can be input to produce that code ideally 1 LSB A specification of 1 LSB differential nonlinearity ensures that no code has a width of 0 LSBs that is no missing codes and that no code width exceeds 2 LSBs System noise is the amount of noise seen by the ADC when there is no signal present at the input of the board The amount of noise that is reported directly without a...

Page 48: ...uracy encompasses both nonlinearity and quantization uncertainties Integral nonlinearity is the worst case deviation of the center of the code from the ideal center expressed in terms of LSBs Finally the differential nonlinearity is deviation of a code width from ideal code width expressed in terms of LSBs Figure A 1 ADC Errors Re1 1 x x INLe Re2 2 Output Code LSB 1 1 2 1 2 Cideal Cactual Vactual ...

Page 49: ...ntains a manufacturer data sheet for the MSM82C53 CMOS programmable interval timer OKI Semiconductor This timer is used on the PC LPM 16PnP board Copyright ΟΚΙ Semiconductor 1995 Reprinted with permission of copyright owner All rights reserved OKI Semiconductor Data Book Microprocessor Eight Edition January 1995 ...

Page 50: ...Appendix B MSM82C53 Data Sheet PC LPM 16 PnP User Manual B 2 National Instruments Corporation ...

Page 51: ...Appendix B MSM82C53 Data Sheet National Instruments Corporation B 3 PC LPM 16 PnP User Manual ...

Page 52: ...Appendix B MSM82C53 Data Sheet PC LPM 16 PnP User Manual B 4 National Instruments Corporation ...

Page 53: ...Appendix B MSM82C53 Data Sheet National Instruments Corporation B 5 PC LPM 16 PnP User Manual ...

Page 54: ...Appendix B MSM82C53 Data Sheet PC LPM 16 PnP User Manual B 6 National Instruments Corporation ...

Page 55: ...Appendix B MSM82C53 Data Sheet National Instruments Corporation B 7 PC LPM 16 PnP User Manual ...

Page 56: ...Appendix B MSM82C53 Data Sheet PC LPM 16 PnP User Manual B 8 National Instruments Corporation ...

Page 57: ...Appendix B MSM82C53 Data Sheet National Instruments Corporation B 9 PC LPM 16 PnP User Manual ...

Page 58: ...Appendix B MSM82C53 Data Sheet PC LPM 16 PnP User Manual B 10 National Instruments Corporation ...

Page 59: ...Appendix B MSM82C53 Data Sheet National Instruments Corporation B 11 PC LPM 16 PnP User Manual ...

Page 60: ...Appendix B MSM82C53 Data Sheet PC LPM 16 PnP User Manual B 12 National Instruments Corporation ...

Page 61: ...6 This revised board has the same functionality as the Plug and Play version except for the base address and interrupt selection but differs somewhat from the legacy board The following list compares the specifications and functionality of the newer boards with the obsolete board Table C 1 Comparison of Characteristics Functional Changes Legacy PC LPM 16 Revised PC LPM 16 PC LPM 16PnP Assembly Num...

Page 62: ...it 1 Status Register 2 bit 1 Overrun Error Bit Location Not implemented Not implemented Status Register 2 bit 0 Data Error Bit Location Not implemented Not implemented Status Register 1 bit 1 5 and 12 V Supply Fuses Nonresettable Self resetting Self resetting 12 V Supply Power Requirements 0 mA 15 mA typ 15 mA typ Performance Specification Changes INL 1 LSB max 0 5 LSB max 0 5 LSB max Gain Error 2...

Page 63: ... to the assembly number displayed on your circuit board see Figure C 1 Interrupt Enable Disable Control Through Command Register 1 Through Command Register 1 Through Plug and Play BIOS or NI DAQ Configuration Utility Delay Between Rising EXTCONV Edge and A D Conversion 2 4 µs 800 ns max 800 ns max Table C 1 Comparison of Characteristics Continued Functional Changes Legacy PC LPM 16 Revised PC LPM ...

Page 64: ...ers W1 and W2 configure the analog input circuitry The DIP switch and jumpers are shown in the parts locator diagram in Figure C 1 The PC LPM 16 is factory configured to a base I O address of hex 260 and to interrupt level 5 These settings shown in Table C 1 are suitable for most systems However if your system has other hardware at this base I O address or interrupt level you need to change these ...

Page 65: ...r PC LPM 16 Non PnP Board National Instruments Corporation C 5 PC LPM 16 PnP User Manual Figure C 1 PC LPM 16 Parts Locator Diagram 1 W3 2 Switch U26 3 W2 4 W1 5 Serial Number 6 Assembly Number 7 Product Name 2 3 4 6 7 5 1 ...

Page 66: ... that this base I O address space is not already used by other equipment installed in your computer Note If any equipment in your computer already uses this base I O address space you must change the base I O address of the PC LPM 16 or of the other device If you change the PC LPM 16 base I O address you must make a corresponding change to any software packages you use with the PC LPM 16 For more ...

Page 67: ...he five LSBs of the address A4 through A0 to select the appropriate PC LPM 16 register To change the base I O address 1 Remove the plastic cover on U26 2 Slide each switch to the desired position 3 Check each switch to verify that the switch is pressed entirely to the side 4 Replace the plastic cover Note the new PC LPM 16 base I O address for use when configuring the PC LPM 16 software in the Har...

Page 68: ... O Address Space Switch Setting Base I O Address hex Base I O Address Space Used hex A9 A8 A7 A6 A5 0 1 0 0 0 100 100 10F 0 1 0 0 1 120 120 13F 0 1 0 1 0 140 140 14F 0 1 0 1 1 160 160 16F 0 1 1 0 0 180 180 18F 0 1 1 0 1 1A0 1A0 1AF 0 1 1 1 0 1C0 1C0 1CF 0 1 1 1 1 1E0 1E0 1EF 1 0 0 0 0 200 200 20F 1 0 0 0 1 220 220 22F 1 0 0 1 0 240 240 24F 1 0 0 1 1 260 260 26F 1 0 1 0 0 280 280 28F 1 0 1 0 1 2A0 ...

Page 69: ...interrupt lines that the PC LPM 16 hardware supports are IRQ 3 7 and IRQ9 Note Using interrupt line 6 is not recommended The diskette drive controller uses interrupt line 6 on most IBM PC and compatible computers After you select an interrupt level place the interrupt jumper on the appropriate pins to enable the interrupt line The interrupt jumper setting is W3 The default interrupt line is IRQ5 w...

Page 70: ...channel Figure C 4 Interrupt Jumper Setting for Disabling Interrupts Analog Input Jumper Settings The PC LPM 16 is factory configured for the 5 V input range Four ranges are available for analog input bipolar 5 V bipolar 2 5 V unipolar 0 to 10 V and unipolar 0 to 5 V Jumpers W1 and W2 control the input range for all 16 analog input channels Bipolar Input Selection 1 5 V Select the bipolar 5 V inpu...

Page 71: ...2 5 V Select the bipolar 2 5 V input configuration by setting jumpers W1 and W2 as shown in Figure C 6 Figure C 6 Bipolar Input 2 5 V Jumper Configuration Unipolar Input Selection 1 0 to 10 V Select the unipolar 0 to 10 V input configuration by setting jumpers W1 and W2 as shown in Figure C 7 Figure C 7 Unipolar Input 0 to 10 V Jumper Configuration W1 C B A W2 C B A W1 C B A W2 C B A C B A C B A W...

Page 72: ...xpansion slot in your computer To optimize the board noise performance install the board away from the video card and leave a slot vacant on each side of the PC LPM 16 if possible After you make any necessary changes with the jumper and switch settings you are ready to install the PC LPM 16 The following are general installation instructions but consult your computer user manual or technical refer...

Page 73: ...1 This table gives the register name the register address offset from the board s base address the type of the register read only write only or read and write and the size of the register in bits Table D 1 PC LPM 16 PnP Register Map Register Name Offset Address Hex Type Size Configuration and Status Register Group Command Register 1 Command Register 2 Command Register 3 Status Register 1 Status Re...

Page 74: ...LPM 16 PnP and the D A circuitry The Analog Input Register Group reads output from the successive approximation ADC The Counter Timer Register Group accesses the onboard MSM82C53 counter timer integrated circuit The Digital I O Register Group consists of the digital output and input registers Counter Timer MSM82C53 Register Group Counter 0 Data Register Counter 1 Data Register Counter 2 Data Regis...

Page 75: ...ial note of the bits labeled reserved for future use The board may not function if you don t write the designated value to these register bits The bit map field for some write only registers states not applicable no bits used Writing to these registers causes an event to occur on the PC LPM 16PnP such as clearing the analog input circuitry The data is ignored when writing to these registers theref...

Page 76: ...etting SCANEN to 1 To set up a scanning mode two consecutive writings of this register are necessary First write the desired valve to the UP DOWN bit in Command Register 2 if the UP DOWN bit is not currently set to its proper value Then write MA 3 0 with SCANEN set to load the scan counter Then write MA 3 0 with SCANEN cleared to enable scanning For example if the UP DOWN bit is 0 and MA 3 0 is 00...

Page 77: ...bit is set the external interrupt is enabled The external device that asserts this signal is responsible for keeping EXTINT low until the interrupt is acknowledged and is then responsible for releasing it EXTINT is pulled up to 5 V on the board 4 FIFOINTEN First In First Out Interrupt Enable Bit This bit enables and disables the interrupt generation when A D conversion results are available The po...

Page 78: ... by the SCANORDER bit in Command Register 2 If SCANEN is set a single analog channel specified by MA 3 0 is sampled during the entire data acquisition operation See the Programming Multiple A D Conversions with Channel Scanning section later in this appendix for the correct sequence involved in setting the SCANEN bit MA 3 0 Selected Channel 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11...

Page 79: ...nel 0 and ends with the channel number in MA 3 0 This bit is cleared upon power up To ensure proper scanning this bit should be correctly programmed before writing to the SCANEN and Channel Selection bits in Command Register 1 This bit is only present on the PC LPM 16PnP Note The UP function is not yet supported by NI DAQ NI DAQ will support the UP function in a future release 1 DISABDAQ Disable D...

Page 80: ... is enabled The power on value is 0 To start the auto calibration first write one to this bit then read this register The result of the reading is ignored An auto calibration lasts about 10 ms By checking the CONVPROG bit of the Status Register the completion of auto calibration can be detected After the auto calibration you must clear this bit for the A D conversion operation a Book l Appendix D ...

Page 81: ...ly Word Size 8 bit Bit Map Bit Name Description 7 2 0 Reserved Bits These bits must be set to zero 1 0 ARNG 1 0 Analog Input Voltage Range These bits control the analog input voltage range setting as follows The power on value for ARNG 1 0 is 10 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ARNG 1 ARNG 0 ARNG 1 0 Input Voltage Range 00 0 to 10 V 10 5 V 0 to 5 V 11 2 5 V a Book l Appendix D Page 9 Wednesday November...

Page 82: ...dentifies the board revision If this bit is cleared the board is a revision A legacy PC LPM 16 board If this bit is set the board is a revision B or later PC LPM 16 board The revision B board has one more bit in Command Register 2 to disable the data acquisition operation This bit is always set for the PC LPM 16PnP board 6 5 X Don t care bits 4 CONVPROG Conversion Progress Status Bit When an A D c...

Page 83: ... set a low to high transition on counter 2 output sets this bit and generates an interrupt request Clear this bit by writing to the CNTINTCLR Register 1 DATAERR OVERFLOW Data Error Overflow Bit This bit indicates if an overflow or overrun error has occurred On the PC LPM 16PnP this bit is the data error bit If this bit is cleared no error was encountered If this bit is set the A D FIFO has overflo...

Page 84: ...s finished with the last conversion and the result can be read from the FIFO This bit is cleared if the FIFO is empty Writing to the ADCLR Register sets this bit on the PC LPM 16 only You need a FIFO low and high bytes reading to completely empty the PC LPM 16 FIFO On the PC LPM 16PnP the DAVAIL bit always exactly represents whether data is in the FIFO a Book l Appendix D Page 12 Wednesday Novembe...

Page 85: ... has overflowed because the data acquisition servicing operation could not keep up with the sampling rate To clear this bit write to the A D Clear Register 0 OVERRUN Overrun Bit This bit indicates whether an A D conversion was initiated before the previous A D conversion was complete OVERRUN is an error condition that will occur if the data acquisition sample interval is too small sample rate is t...

Page 86: ...ter Group control the analog input circuitry and can be used to read the FIFO Reading the FIFO Register returns stored A D conversion results Writing to the A D Clear Register clears the data acquisition circuitry Bit descriptions for the registers making up the Analog Input Register Group are given on the following pages a Book l Appendix D Page 14 Wednesday November 20 1996 6 36 PM ...

Page 87: ...is empty after reading all the values it contains The Status Register should be checked before the A D FIFO Register is read If the A D FIFO contains one or more A D conversion values the DAVAIL bit is set in the Status Register and the external device can read the A D FIFO Register to retrieve a value If the DAVAIL bit is cleared the A D FIFO is empty in which case reading the A D FIFO Register r...

Page 88: ...0 A D Conversion Data Bits 7 through 0 These bits contain the low byte of the 16 bit sign extended two s complement result of a 12 bit A D conversion Note The ADC resolution is actually 13 bits not 12 bits NI DAQ only returns a 12 bit value and the PC LPM 16 PnP boards are tested only to 12 bit accuracy However by writing register level programming you can use the full 13 bits The ADC always retur...

Page 89: ...e cleared as well For the PC LPM 16 non PnP only writing to this register clears the data FIFO and loads a single conversion into the FIFO After writing to the A D Clear Register it is necessary to read both the High and Low Byte FIFOs The data that is read back should be ignored Address Base address 01 hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used a Book l Appendix D Pag...

Page 90: ...sition timing and all three counters are available for general purpose timing functions The MSM82C53 has three independent 16 bit counters and one 8 bit Mode Register The Mode Register sets the mode of operation for each of the three counters Writing to the Timer Interrupt Clear Register clears the interrupt request asserted when a low pulse is detected on the output of counter 2 Bit descriptions ...

Page 91: ...ter 0 Data Register to load and read back contents of MSM82C53 counter 0 Address Base address 08 hex Type Read and write Word Size 8 bit Bit Map Bit Name Description 7 0 D 7 0 A D Conversion Data Bits 7 through 0 8 bit counter 0 contents 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 a Book l Appendix D Page 19 Wednesday November 20 1996 6 36 PM ...

Page 92: ...cription 7 0 D 7 0 A D Conversion Data Bits 7 through 0 8 bit counter 1 contents Counter 2 Data Register Use the Counter 2 Data Register to load and read back contents of MSM82C53 counter 2 Address Base address 0A hex Type Read and write Word Size 8 bit Bit Map Bit Name Description 7 0 D 7 0 A D Conversion Data Bits 7 through 0 8 bit counter 2 contents 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 7 6 5...

Page 93: ...of the MSM82C53 and the counting mode binary or BCD The Counter Mode Register is an 8 bit register Bit descriptions for each of these bits are included in Appendix B MSM82C53 Data Sheet Address Base address 0B hex Type Write only Word Size 8 bit Bit Map Bit Name Description 7 6 SC 1 0 Counter Select Bits These bits select the counter on which the command operates 7 6 5 4 3 2 1 0 SC1 SC0 RL1 RL0 M2...

Page 94: ...Counter Latch command The Counter Latch command latches the current count of the register selected by SC1 and SC0 The next read from the selected counter returns the latched data RL1 RL0 Operation 0 0 Counter Latch command 0 1 Read and write least significant byte only 1 0 Read and write most significant byte only 1 1 Read and write least significant byte then most significant byte a Book l Append...

Page 95: ...pendix B MSM82C53 Data Sheet for additional information 0 BCD Binary Coded Decimal Select Bit If BCD is set the selected counter keeps count in BCD If BCD is cleared the selected counter keeps count in 16 bit binary M2 M1 M0 Mode 0 0 0 Mode 0 Interrupt on terminal count 0 0 1 Mode 1 Hardware retriggerable one shot 0 1 0 Mode 2 Rate generator 0 1 1 Mode 3 Square wave mode 1 0 0 Mode 4 Software retr...

Page 96: ...utput lines of the I O connector The Digital Input Register returns the digital state of the eight digital input lines of the I O connector Bit descriptions for the register in the Digital I O Register Group follow Digital Output Register Write to the Digital Output Register to control the eight digital output lines of the I O connector The pattern contained in the Digital Output Register is drive...

Page 97: ...logic state of the I O connector s eight digital input lines Address Base address 05 hex Type Read only Word Size 8 bit Bit Map Bit Name Description 7 0 D 7 0 8 Bit Input Data Bit These eight bits represent the logic state of the digital input lines DIN 0 through DIN 7 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 a Book l Appendix D Page 25 Wednesday November 20 1996 6 36 PM ...

Page 98: ...register bits without changing the current state of the remaining bits in the register However writing to these registers affects all register bits simultaneously You cannot read these registers to determine which bits have been set or cleared in the past therefore you should maintain a software copy of the write only registers You can then read this software copy to determine the status of the wr...

Page 99: ... calibration cycle 2 Read Command Register 2 to start the self calibration cycle and ignore the result of the reading 3 Read the Status Register and check the CONVPROG bit After starting the self calibration checking this bit can detect the completion of the self calibration cycle A one in this bit indicates the calibration is in progress and zero indicates the completion of the calibration 4 Afte...

Page 100: ...ter first then read the A D FIFO High Byte Register to get the result The first reading returns the low byte of 16 bit data and the second reading returns the high byte Reading the Low and High Byte A D FIFO Registers removes the A D conversion result from the A D FIFO The DAVAIL bit indicates whether one or more A D conversion results are stored in the A D FIFO If the DAVAIL bit is cleared the A ...

Page 101: ... by two to yield a 12 bit resolution reading Also if you want the full 13 bit resolution can be used with the bipolar ranges Notice however that in Appendix A Specifications LSB refers to the least significant bit of a 12 bit conversion value Table D 2 shows input voltage versus A D conversion values for the 0 to 10 V input range Table D 3 shows input voltage versus A D conversion values for 5 to ...

Page 102: ...og input circuitry and the A D FIFO Write 0 to the A D Clear Register 8 bit write Programming Multiple A D Conversions on a Single Input Channel Using Counter 0 This manual refers to a sequence of timed A D conversions as a data acquisition operation Counter 0 of the MSM82C53 is used as the sample interval counter In a data acquisition operation counter 0 continuously generates the conversion puls...

Page 103: ...tput initiates a conversion You can program counter 0 to generate a pulse once every N µs N is referred to as the sample interval that is the time between successive A D conversions N can be between 20 and 65 535 The sample interval is equal to the period of the timebase clock used by counter 0 multiplied by N A 1 MHz clock is internally connected to CLK0 the clock used by counter 0 Use the follow...

Page 104: ...ice the data acquisition operation This topic is discussed in the A D Interrupt Programming section later in this appendix An overflow error condition may occur during a data acquisition operation This error condition is reported through the Status Register and the overflow should be checked every time the Status Register is read An overflow condition occurs if more than 256 A D conversions have b...

Page 105: ... Counter Mode Register to force OUT0 high enable EXTCONV Writing 30 to the Counter Mode Register forces OUT0 low which disables the EXTCONV and stops the data acquisition operation 3 Select the analog input channel Write to Command Register 1 to select the analog input channel The SCANEN bit must be set for data acquisition operation on a single channel See Command Register 1 bit descriptions earl...

Page 106: ... fast enough to keep up with the A D conversion rate When an overflow occurs you lose at least one A D conversion result An overflow condition has occurred if you clear the OVERFLOW bit in the Status Register Reset the OVERFLOW bit in the Status Register by writing to the A D Clear Register Programming Multiple A D Conversions with Channel Scanning The data acquisition programming sequences given ...

Page 107: ...ed during the second write to Command Register 1 Use either counter 0 or EXTCONV to control the scanning interval A D Interrupt Programming You can use an interrupt to service the data acquisition operation To use the conversion interrupt set the FIFOINTEN bit in Command Register 1 If this bit is set an interrupt is generated whenever the DAVAIL bit in the Status Register is set Clear this interru...

Page 108: ...except the CLK0 signal of counter 1 are available for general purpose timing applications Counter 0 has a fixed 1 MHz clock input and can be used as the sample interval counter of A D conversion Write and read operations to the MSM82C53 are 8 bit operations For general programming details refer to Appendix B MSM82C53 Data Sheet a Book l Appendix D Page 36 Wednesday November 20 1996 6 36 PM ...

Page 109: ...tions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers updates and example programs For ...

Page 110: ...your software to obtain support Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 79 90 19 Belgium 02 757 00 20 02 757 03 11 Canada Ontario 905 785 0085 905 785 0086 Canada Quebec 514 694 8521 514 694 4399 Denmark 45 76 26 00 45 76 26 02 Finland 09 527 2321 09 502 2930 France 01 48 14 24 24 01 48 14 24 14 Germany 089 741 31 30 089 714 60 35 Hong Kong 2645 3186 2686 ...

Page 111: ...________________ _______________________________________________________________________________ National Instruments hardware product model___________ Revision_______________________ Configuration ___________________________________________________________________ National Instruments software product____________________________ Version_____________ Configuration _________________________________...

Page 112: ...dress of other boards _________________________________________________ DMA channels of other boards __________________________________________________ Interrupt level of other boards ___________________________________________________ Other Products Computer make and model ______________________________________________________ Microprocessor _______________________________________________________...

Page 113: ...________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________...

Page 114: ...egrees negative of or minus Ω ohms per percent plus or minus positive of or plus square root of 5 V 5 VDC source signal Prefix Meaning Value p pico 10 12 n nano 10 9 µ micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 109 a Book n Glossary Page 1 Wednesday November 20 1996 6 36 PM ...

Page 115: ...nput ground signal AISENSE analog input sense signal ANSI American National Standards Institute AOGND analog output ground signal ASIC application specific integrated circuit AWG American Wire Gauge B BBS bulletin board support BCD binary coded decimal BIOS basic input output system or built in operating system C C Celsius cm centimeter CMOS complementary metal oxide semiconductor a Book n Glossar...

Page 116: ...t current DMA direct memory access E EISA Extended Industry Standard Architecture ESP Engineering Software Package F F farads FIFO first in first out ft feet H h hour hex hexadecimal Hz hertz I I O input output IOH current output high IOL current output low a Book n Glossary Page 3 Wednesday November 20 1996 6 36 PM ...

Page 117: ...bit M m meter MB megabytes of memory MSB most significant bit P PC personal computer R RAM random access memory rms root mean square S s seconds S samples SCANCLK scan clock signal SCXI Signal Conditioning eXtensions for Instrumentation SISOURCE SI counter clock signal STARTSCAN start scan signal a Book n Glossary Page 4 Wednesday November 20 1996 6 36 PM ...

Page 118: ... User Manual T TTL transistor transistor logic V V volts VDC volts direct current VI virtual instrument VIH volts input high VIL volts input low Vin volts in VOH volts output high VOL volts output low a Book n Glossary Page 5 Wednesday November 20 1996 6 36 PM ...

Page 119: ...e circuitry D 30 programming sequence D 28 theory of operation 3 5 to 3 6 analog input jumper settings PC LPM 16 C 10 to C 12 bipolar input selection 1 5 V C 10 to C 11 bipolar input selection 2 2 5 V C 11 unipolar input selection 1 0 to 10 V C 11 unipolar input selection 2 0 to 5 V C 12 Analog Input Register Group A D Clear Register D 17 A D FIFO Low Byte Register and A D FIFO High Byte Register ...

Page 120: ...3 REVID D 10 RL 1 0 D 22 SC 1 0 D 21 SCANEN D 4 D 33 D 34 to D 35 SCANORDER D 7 block diagram of PC LPM 16PnP 3 2 board configuration See configuration bulletin board support E 1 bus interface specifications A 4 C cables custom 1 5 to 1 6 CALEN bit D 8 D 28 calibration autocalibration 3 5 to 3 6 programming A D calibration D 27 CLK signal counter block diagram 3 10 general purpose timing and count...

Page 121: ... 19 D 30 to D 32 Counter 1 Data Register D 20 Counter 2 Data Register D 20 Counter Mode Register D 21 to D 23 overview D 18 programming D 36 register map D 2 Timer Interrupt Clear Register D 24 custom cables 1 5 to 1 6 customer communication xii E 1 to E 2 D D 7 0 bits Counter 0 Data Register D 19 Counter 1 Data Register D 20 Counter 2 Data Register D 20 Digital Input Register D 25 Digital Output ...

Page 122: ... 5 F fax and telephone support E 2 FaxBack support E 2 FIFOINTEN bit D 5 D 35 frequency measurement 4 10 to 4 11 FTP support E 1 fuse self resetting table 4 8 G GATE signal counter block diagram 3 10 general purpose timing and counter timing 4 9 to 4 12 timing requirements for GATE and CLK input signals 4 11 to 4 12 GATE0 signal table 4 4 GATE1 signal table 4 4 GATE2 signal table 4 4 general purpo...

Page 123: ...put 3 5 N NI DAQ driver software 1 3 to 1 4 O operation of PC LPM 16PnP See theory of operation OUT signal counter block diagram 3 10 general purpose timing and counter timing 4 9 to 4 12 timing specifications for OUT output signals 4 11 to 4 12 OUT0 signal table 4 4 OUT1 signal table 4 4 OUT1 signal table 4 3 OUT2 signal table 4 4 OVERFLOW bit description D 13 register level programming D 28 D 32...

Page 124: ... D FIFO Low Byte Register and A D FIFO High Byte Register D 15 to D 16 overview D 14 Configuration and Status Register Group Command Register 1 D 4 to D 6 Command Register 2 D 7 to D 8 Command Register 3 D 9 overview D 3 Status Register 1 D 10 to D 12 Status Register 2 D 13 Counter Timer MSM82C53 Register Group Counter 0 Data Register D 19 D 30 to D 32 Counter 1 Data Register D 20 Counter 2 Data R...

Page 125: ...ents A 4 timing I O A 3 square wave generation 4 9 Status Register 1 D 10 to D 12 Status Register 2 D 13 switch settings See configuration system noise A 5 T technical support E 1 to E 2 theory of operation analog input circuitry 3 5 to 3 6 block diagram 3 4 block diagram 3 2 data acquisition timing circuitry 3 6 to 3 7 block diagram 3 5 data acquisition rates 3 7 multichannel scanning data acquis...

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