NI sbRIO-961x/9612XT/963x/9632XT/964x/9642XT
24
ni.com
Integrated 3.3 V Digital I/O
The four 50-pin IDC headers, P2–P5, provide connections for
110 low-voltage DIO channels, 82 D GND, and eight +5 V voltage outputs.
Figure 16 represents a single DIO channel.
Figure 16.
Circuitry of One 3.3 V DIO Channel
I/O Protection
The 33
Ω
current-limiting posistor, R1, and the protection diodes, D1 and
D2, protect each DIO channel against externally applied voltages and ESD
events. The combination of R1 and D1 protects against overvoltage,
and the combination of R1 and D2 protects against undervoltage. The
resistance of R1 increases rapidly with temperature. During overvoltage
conditions, high current flows through R1 and into the protection diodes.
High current causes internal heating in the posistor, which increases the
resistance and limits the current. Refer to the
section for
current-limiting and resistance values.
Drive Strength
The NI sbRIO devices are tested with all 110 DIO channels driving 3 mA
DC loads, for a total of 330 mA sourcing from the FPGA. The FPGA uses
minimum 8 mA drivers, but the devices are not characterized for loads
higher than 3 mA.
U1: 5 V to
3
.
3
V Level Shifter, SN74CBTD
338
4CDGV from Tex
as
In
s
tr
u
ment
s
D1
a
nd D2: ESD-R
a
ted Protection Diode
s
, NUP4
3
02MR6T1G from ON Semicond
u
ctor
R1: C
u
rrent-Limiting Po
s
i
s
tor, PRG1
8
BB
33
0MS1RB from M
u
r
a
t
a
User
Connection
Xilinx
S
partan-3 FPGA
U1
+5 V
D2
D1
R1
