Figure 7. Connecting to the DIO Channels
NI PCIe-7846
Power
FPGA
Connection
Accessory
DIO0
DIO1
DIO14
DIO15
Connecter 0 (MIO)
1
Connection
Accessory
DIO0
DIO1
DIO30
DIO31
Connecter 1 (DIO)
2
3
1. Low-speed signal frequencies up to 10 MHz with logic levels configured as 1.2 V, 1.5 V, 1.8 V, 2.5 V, or
3.3 V.
2. High-speed signal frequencies up to 80 MHz with logic levels configured as 1.2 V, 1.5 V, 1.8 V, 2.5 V, or
3.3 V.
3. LED
The DIO channels have overvoltage and undervoltage protection as well as over current
protection. Refer to the device specifications on
for more information about
the maximum voltage and current.
When the system powers on, the DIO channels are set as input low with pull-down resistors.
To set another power-on state, you can configure the NI PCIe-7846 to load a VI when the
system powers on. The VI can then set the DIO lines to any power-on state.
All the high-speed DIO channels on Connector 1 are routed with a 50 Ω characteristic trace
impedance. Route all external circuitry with a similar impedance to ensure best signal quality.
NI recommends performing signal integrity measurements to test the affect of signal routing
with the cable and connection accessory for your application.
Field Wiring Considerations
Environmental noise can seriously affect the measurement accuracy of the device if you do not
take proper care when running signal wire between signal sources and the device. The
following recommendations mainly apply to AI signal routing to the device, as well as signal
routing in general.
6
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NI PCIe-7846 User Manual
