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National Instruments Corporation
9
8-Slot NI PXIe-1062Q Backplane Installation Guide
PXIe_SYNC_CTRL
PXIe_SYNC100 is by default a 10 ns pulse synchronous to PXI_CLK10.
The frequency of PXIe_SYNC100 is 10/
n
MHz, where
n
is a positive
integer. The default for
n
is 1, giving PXIe_SYNC100 a 100 ns period.
However, the backplane allows
n
to be programmed to other integers. For
example, setting
n
= 3 creates a PXIe_SYNC100 with a 300 ns period while
still maintaining its phase relationship to PXI_CLK10. The
n
value can be
any positive integer from 1 to 255.
The system timing slot has a control pin for PXIe_SYNC100 called
PXIe_SYNC_CTRL, for use when
n
> 1. Refer to Table 9,
Pinout for the System Timing Slot
, for the system timing slot pinout. Refer
for the PXIe_SYNC_CTRL input
specifications.
By default, a high level detected by the backplane on the
PXIe_SYNC_CTRL pin causes a synchronous restart for the
PXIe_SYNC100 signal. On the next PXI_CLK10 edge, the
PXIe_SYNC100 signal restarts. This allows several chassis to have their
PXIe_SYNC100 in phase with each other. Refer to Figure 6 for timing
details with this method.
Figure 6.
PXIe_SYNC100 at 3.33 MHz Using PXIe_SYNC_CTRL as Restart
Mechanical Requirements
Mounting
Figure 7 shows the backplane dimensions. There are 24 holes available for
mounting with M2.5 hardware.
Use all mounting holes for proper backplane support.
Two mounting holes on top of the backplane have plated annular pads on
the front and back of the backplane. Use these mounting holes to connect
the backplane ground to the chassis in which the backplane is mounted. If
you do not want to connect the backplane ground to the chassis, use
insulated washers at these mounting holes. Refer to Figure 9 for the
mounting hole positions.
PXI_CLK10
PXIe_SYNC_CTRL
PXIe_SYNC100
SYNC100 Divider
Restarted Here
